bootarm.s

MTK debug flash 兼容性的code

SUP_MODE                EQU      &13         ; Supervisor Mode (SVC)
                                            
IRQ_MODE                EQU      &12         ; Interrupt Mode (IRQ)
FIQ_MODE                EQU      &11         ; Fast Interrupt Mode (FIQ)
ABORT_MODE              EQU      &17         ; Abort Mode (Abort)
UND_MODE                EQU      &1b         ; Undefine Mode (Undefine)
SYS_MODE                EQU      &1f         ; System Mode (SYS)
                                            
TIMER_PRIORITY          EQU      2           ; Timer HISR priority (values from
                                            
I_BIT                   EQU      &80         ; Interrupt bit of CPSR and SPSR
F_BIT                   EQU      &40         ; Interrupt bit of CPSR and SPSR
INT_BIT                 EQU      &C0         ; Interrupt bits
T_BIT                   EQU      &20         ; Thumb mode control bit

UNDEF_EXCEPTION_TYPE    EQU      1           ; Undefine instruction exception type
SWI_EXCEPTION_TYPE      EQU      2           ; SWI exception type
PREFETCH_EXCEPTION_TYPE EQU      3           ; Preftech abort exception type
DATA_EXCEPTION_TYPE     EQU      4           ; Data abort exception type

BOOTROM_FLASH_REMAP     EQU      &02
FLASH_SRAM_REMAP        EQU      &03

IRQ_STACK_SIZE          EQU      128
FIQ_STACK_SIZE          EQU      128
OTHER_STACK_SIZE        EQU      128
EX_STACK_SIZE           EQU      2048
SYS_STACK_SIZE          EQU      2048
TIMER_SIZE              EQU      512

ABNORMAL_POOL_SIZE      EQU      16

; If assembled with TASM the variable {CONFIG} will be set to 16
; If assembled with ARMASM the variable {CONFIG} will be set to 32
; Set the variable THUMB to TRUE or false depending on whether the
; file is being assembled with TASM or ARMASM.

        GBLL    THUMB
        GBLL    ARM
    [ {CONFIG} = 16
THUMB   SETL    {TRUE}
ARM     SETL    {FALSE}

; If assembling with TASM go into 32 bit mode as the Armulator will
; start up the program in ARM state.

        CODE32
    |
THUMB   SETL    {FALSE}
ARM     SETL    {TRUE}
    ]


   IF  (:LNOT: :DEF: REMAPPING)
      GBLL         REMAPPING
REMAPPING   SETL    {FALSE}
   ENDIF

   IF  (:LNOT: :DEF: KAL_ON_NUCLEUS)
      GBLL         KAL_ON_NUCLEUS
KAL_ON_NUCLEUS   SETL    {FALSE}
   ENDIF

   IF  (:LNOT: :DEF: KAL_ON_THREADX)
      GBLL         KAL_ON_THREADX
KAL_ON_THREADX   SETL    {FALSE}
   ENDIF
   
   IF  (:LNOT: :DEF: DCM_ENABLE)
      GBLL         DCM_ENABLE
DCM_ENABLE   SETL    {FALSE}
	ENDIF

   IF  (:LNOT: :DEF: __CHIP_VERSION_CHECK__)
      GBLL         __CHIP_VERSION_CHECK__
__CHIP_VERSION_CHECK__   SETL    {FALSE}
   ENDIF


   AREA |C$$data|, DATA, READWRITE
   
   EXPORT  INT_Loaded_Flag
INT_Loaded_Flag
   DCD      &00000000
   
   EXPORT   INT_Exception_Type
INT_Exception_Type
   DCD      &00000000

;/* Define the global system stack variable.  This is setup by the
;   initialization routine.  */
;

   AREA |STACK_POOL_EXTSRAM|, DATA, READWRITE, ALIGN=3

ABT_Stack_Pool
   SPACE    OTHER_STACK_SIZE

UND_Stack_Pool
   SPACE    OTHER_STACK_SIZE

EX_Stack_Pool
   SPACE    EX_STACK_SIZE

   AREA |STACK_POOL_INTSRAM|, DATA, READWRITE, ALIGN=3
  
IRQ_Stack_Pool
   SPACE    IRQ_STACK_SIZE

FIQ_Stack_Pool
   SPACE    FIQ_STACK_SIZE

   EXPORT   SYS_Stack_Pool
SYS_Stack_Pool
   DCB      "STACKEND"
   SPACE    SYS_STACK_SIZE-8

TMD_Stack_Pool
   DCB      "STACKEND"
   SPACE    TIMER_SIZE-8
      
Abnormal_info_Pool
   SPACE    ABNORMAL_POOL_SIZE

   AREA |DUMMY_POOL|, DATA, READWRITE
DUMMY_END
   DCD      0x454E4400
   
;/* for single bank support */

   IF  (:LNOT: :DEF: SINGLE_BANK_SUPPORT)
      GBLL         SINGLE_BANK_SUPPORT
SINGLE_BANK_SUPPORT   SETL    {FALSE}
   ENDIF

   AREA |C$$code|, CODE, READONLY
|x$codeseg|

;
;
;/* Define the global data structures that need to be initialized by this
;   routine.  These structures are used to define the system timer management
;   HISR.  */
;
;

   IF KAL_ON_NUCLEUS

;extern VOID     *TMD_HISR_Stack_Ptr;
;extern UNSIGNED  TMD_HISR_Stack_Size;
;extern INT       TMD_HISR_Priority;
;extern VOID   *TCD_System_Stack;
;extern VOID   *TCD_Current_Thread;
;extern VOID   INC_Initialize(VOID *first_available_memory);
;extern VOID   TCT_Interrupt_Context_Save(VOID);
;extern VOID   TCT_Interrupt_Context_Restore(VOID);

   IMPORT  TMD_HISR_Stack_Ptr
   IMPORT  TMD_HISR_Stack_Size
   IMPORT  TMD_HISR_Priority
   IMPORT   TCD_System_Stack
   IMPORT   TCT_System_Limit
   IMPORT   TCT_Interrupt_Context_Save
   IMPORT   TCT_Interrupt_Context_Restore
   IMPORT   INC_Initialize   

   ELSE

   IMPORT   _tx_thread_system_stack_ptr
   IMPORT   _tx_thread_context_save
   IMPORT   _tx_thread_irq_nesting_start
   IMPORT   _tx_thread_irq_nesting_end
   IMPORT   _tx_thread_context_restore
   IMPORT   _tx_initialize_kernel_enter

   ENDIF

   IMPORT   INT_SystemReset_Check 
   IMPORT   INT_Config
   IMPORT   INT_InitRegions
   IMPORT   custom_setAdvEMI
   IMPORT   CacheInit
   IMPORT   isrC_Main
   IMPORT   isrCTIRQ1
   IMPORT   INT_FIQ_Lisr
   IMPORT   processing_irqlr
   IMPORT   processing_fiqlr
   IMPORT   stack_system_error
   IMPORT   INT_Exception_SP
   IMPORT   rand_num_seed
   IMPORT GetmemoryInformation

   IF DCM_ENABLE
   IMPORT  DCM_Recovery
   ENDIF

   IF __CHIP_VERSION_CHECK__
   IMPORT   INT_Version_Check
   ENDIF

   IMPORT   SST_DTLB_Init

   IF :DEF:__ROMSA_SUPPORT__  
   IMPORT InitRegions2   
   IMPORT ROMSA_Init      
   ENDIF                        

   EXPORT  DisableIRQ
   EXPORT  ReEnableIRQ
   EXPORT  LockIRQ
   EXPORT  RestoreIRQ
   EXPORT  INT_ExceptionSwitchSP
   EXPORT  INT_ExceptionResetSystemSP
   EXPORT  INT_GetCurrentSP

   IF KAL_ON_THREADX
   EXPORT __tx_irq_processing_return
   ENDIF
     
;
;/* Define the ARM60 interrupt vector table, INT_Vectors.  This table is
;   assumed to be loaded or copied to address 0.  If coexistence with a
;   target-resident-monitor program is required, it is important to only
;   copy the IRQ and possibly the FIQ interrupt vectors in this table into
;   the actual table.  The idea is to not mess with the monitor's vectors.  */
;VOID    *INT_Vectors[NU_MAX_VECTORS];
;


   EXPORT  INT_Vectors
INT_Vectors
   IF REMAPPING
      B     INT_Initialize
   ELSE
      LDR   pc,INT_Table
   ENDIF
   LDR   pc,(INT_Table + 4)
   LDR   pc,(INT_Table + 8)
   LDR   pc,(INT_Table + 12)
   LDR   pc,(INT_Table + 16)
   LDR   pc,(INT_Table + 20)
   LDR   pc,(INT_Table + 24)
   LDR   pc,(INT_Table + 28)


   EXPORT   INT_Table
INT_Table

INT_Initialize_Addr  DCD   INT_Initialize
Undef_Instr_Addr     DCD   Undef_Instr_ISR
SWI_Addr             DCD   SWI_ISR
Prefetch_Abort_Addr  DCD   Prefetch_Abort_ISR
Data_Abort_Addr      DCD   Data_Abort_ISR
Undefined_Addr       DCD   0              ; NO LONGER USED
IRQ_Handler_Addr     DCD   INT_IRQ_Parse
FIQ_Handler_Addr     DCD   INT_FIQ_Parse

INT_Table_END

   IF :LNOT::DEF:_NAND_FLASH_BOOTING_

   EXPORT   EXTSRAM_BSS_Limit_Ptr
EXTSRAM_BSS_Limit_Ptr
   IMPORT  |Image$$EXTSRAM$$ZI$$Limit|
   DCD     |Image$$EXTSRAM$$ZI$$Limit|
   
ROM_Base_Ptr
   IMPORT  |Image$$ROM$$Base|
   DCD     |Image$$ROM$$Base|
   
   IF SINGLE_BANK_SUPPORT
EXTSRAM_Base_Ptr
   IMPORT  |Image$$SINGLE_BANK_CODE$$Base|
   DCD     |Image$$SINGLE_BANK_CODE$$Base|
   ELSE
EXTSRAM_Base_Ptr
   IMPORT  |Image$$EXTSRAM$$Base|
   DCD     |Image$$EXTSRAM$$Base|
   ENDIF

INT_Table_END_PTR
   DCD     INT_Table_END

   ENDIF   

Loaded_Flag
   DCD     INT_Loaded_Flag
;

   IF KAL_ON_NUCLEUS
HISR_Stack_Ptr
   DCD     TMD_HISR_Stack_Ptr
;
HISR_Stack_Size
   DCD     TMD_HISR_Stack_Size
;
HISR_Priority
   DCD     TMD_HISR_Priority
;
System_Stack
   DCD     TCD_System_Stack
;
System_Limit
   DCD     TCT_System_Limit
;
   ELSE

System_Stack
   DCD     _tx_thread_system_stack_ptr
;
   ENDIF

BOOT_IRQ_Stack_End 
   DCD     IRQ_Stack_Pool+IRQ_STACK_SIZE-4
;
BOOT_FIQ_Stack_End 
   DCD     FIQ_Stack_Pool+FIQ_STACK_SIZE-4
;
BOOT_ABT_Stack_End 
   DCD     ABT_Stack_Pool+OTHER_STACK_SIZE-4
;
BOOT_UND_Stack_End 
   DCD     UND_Stack_Pool+OTHER_STACK_SIZE-4
;
   EXPORT   BOOT_SYS_Stack_End
BOOT_SYS_Stack_End 
   DCD     SYS_Stack_Pool+SYS_STACK_SIZE-4
;
BOOT_SYS_Stack
   DCD     SYS_Stack_Pool
;
BOOT_EX_Stack_End 
   DCD     EX_Stack_Pool+EX_STACK_SIZE-16
;

   IF KAL_ON_NUCLEUS
BOOT_TMD_Stack
   DCD     TMD_Stack_Pool
;
BOOT_Timer_HISR_Stack_Size
   DCD     TIMER_SIZE
;
   ENDIF

Exception_SP_PTR
   DCD     INT_Exception_SP
;
WATCHDOG_RESTART_REG