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📄 gaganlock.v

📁 Verilog code for Digital lock
💻 V
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module digilock(clk,i,unlock,mode,pass,invalid,reset,iled);input [9:0] i;//input [3:0] s;input mode,clk,reset;output unlock,pass,invalid;output [9:0] iled;//wire [3:0] t;reg [3:0] c,ledc,s,p1,p2,p3,p4,s1,s2,s3,s4,mp1,mp2,mp3,mp4;reg [9:0] ca,iled;reg pass,manclk,unlock,mode1,invalid,reset1;reg [25:0] ctr;reg count;initial begin	c<=0;//        in<=4'b0000;	pass<=0;	manclk<=0;	ledc<=4'b0000;	p1<=0;p2<=1;p3<=2;p4<=3;	s1<=0;s2<=0;s3<=0;s4<=0;	mp1<=p1;mp2<=p2;mp3<=p3;mp4<=p4;//	a<=0;b<=0;c<=0;d<=0;e<=0;f<=0;g<=0;h<=0;	count<=0;	invalid<=0;	reset1<=0;mode1<=0;unlock<=0;endalways @(posedge clk) begin 	ctr<=ctr+1;		if(ctr==20000000)begin		manclk<=~manclk;		pass<=manclk;		ctr<=0;					end	if(manclk) begin		ca<=i;		mode1<=mode;		reset1<=reset;		if(ca[0]) begin			ledc<=4'b0000;			count<=count+1;		iled[0]<=1;		end		else if(ca[1]) begin			ledc<=4'b0001;			count<=count+1;		iled[1]<=1;		end						else if(ca[2]) begin			ledc<=4'b0010;			count<=count+1;		iled[2]<=1;		end						else if(ca[3]) begin			ledc<=4'b0011;			count<=count+1;			iled[3]<=1;		end						else if(ca[4]) begin			ledc<=4'b0100;			count<=count+1;			iled[4]<=1;		end						else if(ca[5]) begin			ledc<=4'b0101;			count<=count+1;		iled[5]<=1;		end						else if(ca[6]) begin			ledc<=4'b0110;			count<=count+1;		iled[6]<=1;		end						else if(ca[7]) begin			ledc<=4'b0111;			count<=count+1;		iled[7]<=1;		end						else if(ca[8]) begin			ledc<=4'b1000;			count<=count+1;		iled[8]<=1;		end										else if(ca[9]) begin			ledc<=4'b1001;			count<=count+1;	iled[9]<=1;		end//		s<=ledc;				if(count==1)begin			s1<=ledc;			ledc<=0;		end			else if(count==2)begin				s2<=ledc;ledc<=0;			end				else if(count==3)begin					s3<=ledc;ledc<=0;				end					else if(count==4)begin						s4<=ledc;ledc<=0;					end		//compare		if(s1==p1 && s2==p2 && s3==p3 && s4==p4 && count<=4 && mode1==0)begin			unlock<=1;			count<=0;			s1<=0;s2<=0;s3<=0;s4<=0;		end		//password change		if(unlock & mode1)begin			if(s1==p1 && s2==p2 && s3==p3 && s4==p4 && count<=4)begin				s1<=0;s2<=0;s3<=0;s4<=0;				count<=0;invalid<=0;			end			else begin				invalid<=1;			end			if(~invalid & mode1)begin				p1<=s1;p2<=s2;p3<=s3;p4<=s4;				s1<=0;s2<=0;s3<=0;s4<=0;mode1<=0;reset1<=0;			end			end		if(reset1==1)begin		   unlock<=0;		iled<=0;			p1<=mp1;p2<=mp2;p3<=mp3;p4<=mp4;			mode1<=0;		end	endend					endmodule

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