📄 k44init.s.bak
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; ************************************************
; * NAME : K44INIT.S *
; * Version : 3.MAY.2000 *
; * Description: *
; * C start up codes *
; * Configure memory, Initialize ISR ,stacks *
; * Initialize C-variables *
; * Fill zeros into zero-initialized C-variables *
; ************************************************
GET option.a
;GCS1 256KB SRAM(0x00800000-0x0083ffff)
;APP RAM=0x00800000~0x0083efff
;41MON RAM:0x0083f000-0x0083ffff
;SVC_STACK:0x0083fd60 (0x083ff80-0x220)
;Interrupt Control
wINTMODE EQU 0x1ffc000
wINTPEND EQU 0x1ffc004
wINTMASK EQU 0x1ffc008
;Watchdog timer
hBTCON EQU 0x1ffa002
;Clock Controller
hSYSCON EQU 0x1ffd002
wPLLCON EQU 0x1ffd004
;Memory Controller
wSYSCFG EQU 0x1ff3000
wMEMCON0 EQU 0x1ff4000
wMEMCON1 EQU 0x1ff4004
wMEMCON2 EQU 0x1ff4008
;Port Control
hP1CON EQU 0x1ffb012
;Pre-defined constants
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f
NOINT EQU 0xc0
;check if tasm.exe is used.
GBLL THUMBCODE
[ {CONFIG} = 16
THUMBCODE SETL {TRUE}
CODE32
|
THUMBCODE SETL {FALSE}
]
[ THUMBCODE
CODE32 ;for start-up code for Thumb mode
]
MACRO
$HandlerLabel HANDLER $HandleLabel
$HandlerLabel
sub sp,sp,#4
stmfd sp!,{r0}
ldr r0,=$HandleLabel
ldr r0,[r0]
str r0,[sp,#4]
ldmfd sp!,{r0,pc}
MEND
IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ; Base of RAM to initialise
IMPORT |Image$$ZI$$Base| ; Base and limit of area
IMPORT |Image$$ZI$$Limit| ; to zero initialise
IMPORT Main
AREA Init,CODE,READONLY
ENTRY
b ResetHandler ;for debug
b HandlerUndef ;handlerUndef
b HandlerSWI ;SWI interrupt handler
b HandlerPabort ;handlerPAbort
b HandlerDabort ;handlerDAbort
b . ;handlerReserved
b HandlerIRQ
b HandlerFIQ
; The follwoing is faster. But,you can't use your own IRQ/FIQ handler.
; b IsrIRQ
; b IsrFIQ
% 0x60 ; To locate the H/W interrupt vector table at 0x00000080
; This area may be used for another purpose.
; But,the size should be exasctly 0x60 bytes.
IRQ_ADDR EQU 0x18
FIQ_ADDR EQU 0x1c
VECTOR_ADDR EQU 0x80
VECTOR_BRANCH ;@0x00000080
;'ldr pc,=xxxx' can not be allowed here
;because the interrupt controller expect branch instruction.
;This is the different things with S3C44B0X.
;The S3C44B0X allows the 'ldr pc,=xxxx'
;If the interrupt is IRQ, subtract 0x18 from the ISR address.
;If the interrupt is FIQ, subtract 0x1c from the ISR address.
b (HandlerURXD +VECTOR_ADDR-IRQ_ADDR+0x0) ;H/W interrupt vector table
b (HandlerUTXD +VECTOR_ADDR-IRQ_ADDR+0x4)
b (HandlerUERR +VECTOR_ADDR-IRQ_ADDR+0x8)
b (HandlerT0OVF +VECTOR_ADDR-IRQ_ADDR+0xc)
b (HandlerT0MC +VECTOR_ADDR-IRQ_ADDR+0x10)
b (HandlerT1OVF +VECTOR_ADDR-IRQ_ADDR+0x14)
b (HandlerT1MC +VECTOR_ADDR-IRQ_ADDR+0x18)
b (HandlerT2OVF +VECTOR_ADDR-IRQ_ADDR+0x1c)
b (HandlerT2MC +VECTOR_ADDR-IRQ_ADDR+0x20)
b (HandlerT3OVF +VECTOR_ADDR-IRQ_ADDR+0x24)
b (HandlerT3MC +VECTOR_ADDR-IRQ_ADDR+0x28)
b (HandlerT4OVF +VECTOR_ADDR-IRQ_ADDR+0x2c)
b (HandlerT4MC +VECTOR_ADDR-IRQ_ADDR+0x30)
b (HandlerT5OVF +VECTOR_ADDR-IRQ_ADDR+0x34)
b (HandlerT5MC +VECTOR_ADDR-IRQ_ADDR+0x38)
b (HandlerBT +VECTOR_ADDR-IRQ_ADDR+0x3c)
b (HandlerEINT0 +VECTOR_ADDR-IRQ_ADDR+0x40)
b (HandlerEINT1 +VECTOR_ADDR-IRQ_ADDR+0x44)
b (HandlerEINT2 +VECTOR_ADDR-IRQ_ADDR+0x48)
LTORG
HandlerFIQ HANDLER HandleFIQ
HandlerIRQ HANDLER HandleIRQ
HandlerUndef HANDLER HandleUndef
HandlerSWI HANDLER HandleSWI
HandlerDabort HANDLER HandleDabort
HandlerPabort HANDLER HandlePabort
HandlerURXD HANDLER HandleURXD
HandlerUTXD HANDLER HandleUTXD
HandlerUERR HANDLER HandleUERR
HandlerT0OVF HANDLER HandleT0OVF
HandlerT0MC HANDLER HandleT0MC
HandlerT1OVF HANDLER HandleT1OVF
HandlerT1MC HANDLER HandleT1MC
HandlerT2OVF HANDLER HandleT2OVF
HandlerT2MC HANDLER HandleT2MC
HandlerT3OVF HANDLER HandleT3OVF
HandlerT3MC HANDLER HandleT3MC
HandlerT4OVF HANDLER HandleT4OVF
HandlerT4MC HANDLER HandleT4MC
HandlerT5OVF HANDLER HandleT5OVF
HandlerT5MC HANDLER HandleT5MC
HandlerBT HANDLER HandleBT
HandlerEINT0 HANDLER HandleEINT0
HandlerEINT1 HANDLER HandleEINT1
HandlerEINT2 HANDLER HandleEINT2
;compact, but slow
;IsrIRQ
sub sp,sp,#4 ;reserved for PC
stmfd sp!,{r8-r10}
ldr r8,=wINTMODE
ldmia r8,{r8-r10} ;r8=wINTMODE,r9=wINTPEND,r10=wINTMASK
mvn r8,r8
and r8,r8,r9
and r8,r8,r10 ;r8 has IRQ,unmasked,pending bit
mov r9,#0
0 movs r8,r8,lsr #1
bcs %F1
add r9,r9,#4
b %B0
1 ldr r10,=HandleURXD
add r10,r10,r9
ldr r10,[r10]
str r10,[sp,#12]
ldmfd sp!,{r8-r10,pc}
;large, but faster
IsrIRQ
sub sp,sp,#4 ;reserved for PC
stmfd sp!,{r8-r10}
ldr r8,=wINTMODE
ldmia r8,{r8-r10} ;r8=wINTMODE,r9=wINTPEND,r10=wINTMASK
mvn r8,r8
and r8,r8,r9
and r8,r8,r10 ;r8 has IRQ,unmasked,pending bit
MACRO
ISIRQ $intBit,$HandlerLabel
tst r8,$intBit
ldrne r9,$HandlerLabel
strne r9,[sp,#12]
ldmnefd sp!,{r8-r10,pc}
MEND
;1) Replace HandlerXXXX to your own handler.
;2) Delete the routine of an unused interrupt.
ISIRQ #0x1, HandlerURXD
ISIRQ #0x2, HandlerUTXD
ISIRQ #0x4, HandlerUERR
ISIRQ #0x8, HandlerT0OVF
ISIRQ #0x10, HandlerT0MC
ISIRQ #0x20, HandlerT1OVF
ISIRQ #0x40, HandlerT1MC
ISIRQ #0x80, HandlerT2OVF
ISIRQ #0x100, HandlerT2MC
ISIRQ #0x200, HandlerT3OVF
ISIRQ #0x400, HandlerT3MC
ISIRQ #0x800, HandlerT4OVF
ISIRQ #0x1000,HandlerT4MC
ISIRQ #0x2000,HandlerT5OVF
ISIRQ #0x4000,HandlerT5MC
ISIRQ #0x8000,HandlerBT
ISIRQ #0x10000,HandlerEINT0
ISIRQ #0x20000,HandlerEINT1
ISIRQ #0x40000,HandlerEINT2
b .
;large, but faster
IsrFIQ
ldr r8,=wINTMODE
ldmia r8,{r8-r10} ;r8=wINTMODE,r9=wINTPEND,r10=wINTMASK
mvn r8,r8
and r8,r8,r9
and r8,r8,r10 ;r8 has IRQ,unmasked,pending bit
MACRO
ISFIQ $intBit,$HandlerLabel
tst r8,$intBit
ldrne pc,HandlerLabel
MEND
ISFIQ #0x1, HandlerURXD
ISFIQ #0x2, HandlerUTXD
ISFIQ #0x4, HandlerUERR
ISFIQ #0x8, HandlerT0OVF
ISFIQ #0x10, HandlerT0MC
ISFIQ #0x20, HandlerT1OVF
ISFIQ #0x40, HandlerT1MC
ISFIQ #0x80, HandlerT2OVF
ISFIQ #0x100, HandlerT2MC
ISFIQ #0x200, HandlerT3OVF
ISFIQ #0x400, HandlerT3MC
ISFIQ #0x800, HandlerT4OVF
ISFIQ #0x1000,HandlerT4MC
ISFIQ #0x2000,HandlerT5OVF
ISFIQ #0x4000,HandlerT5MC
ISFIQ #0x8000,HandlerBT
ISFIQ #0x10000,HandlerEINT0
ISFIQ #0x20000,HandlerEINT1
ISFIQ #0x40000,HandlerEINT2
b .
ResetHandler
ldr r0,=wSYSCFG
ldr r1,=0x1ff0 ; special registers:0x1ffxxxx, STALL_disable
str r1,[r0]
ldr r0,=hBTCON
ldr r1,=0xa503 ; disable w-dog, BT=EXTCLK/2^13, clear BTCNT,
strh r1,[r0]
ldr r0,=wINTMASK
ldr r1,=0x0 ;all interrupt disable
str r1,[r0]
ldr r0,=hSYSCON
ldr r1,=0x118 ;CLKDIVSEL=/1, EXTCLK, PLL_OFF, Global_int_enabled
strh r1,[r0]
;A[17:12] should be configured first of all!!!
; G15 G14 G13 G12 G11 G10 G09 G08
;P1CON :RXD TXD A17 A16 A15 A14 A13 A12
; 00 10, 10 10, 10 10, 10 10
ldr r0,=hP1CON
ldr r1,=0x2aaa
strh r1,[r0]
ldr r0,=SMRDATA
ldmia r0,{r1-r3}
ldr r0,=wMEMCON0
stmia r0,{r1-r3}
bl InitStacks
ldr r0,=HandleIRQ
ldr r1,=IsrIRQ
str r1,[r0]
LDR r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
LDR r1, =|Image$$RW$$Base| ; and RAM copy
LDR r3, =|Image$$ZI$$Base|
;Zero init base => top of initialised data
CMP r0, r1 ; Check that they are different
BEQ %F1
0
CMP r1, r3 ; Copy init data
LDRCC r2, [r0], #4
STRCC r2, [r1], #4
BCC %B0
1
LDR r1, =|Image$$ZI$$Limit| ; Top of zero init segment
MOV r2, #0
2
CMP r3, r1 ; Zero init
STRCC r2, [r3], #4
BCC %B2
[ :LNOT:THUMBCODE
BL Main ;Don't use main() because ......
B .
]
[ THUMBCODE ;for start-up code for Thumb mode
orr lr,pc,#1
bx lr
CODE16
bl Main ;Don't use main() because ......
b .
CODE32
]
InitStacks
;Don't use DRAM,such as stmfd,ldmfd......
;SVCstack is initialized before
;Under toolkit ver 2.50, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
mrs r0,cpsr
bic r0,r0,#MODEMASK
orr r1,r0,#UNDEFMODE|NOINT
msr cpsr_cxsf,r1 ;UndefMode
ldr sp,=UndefStack
orr r1,r0,#ABORTMODE|NOINT
msr cpsr_cxsf,r1 ;AbortMode
ldr sp,=AbortStack
orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 ;IRQMode
ldr sp,=IRQStack
orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 ;FIQMode
ldr sp,=FIQStack
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#SVCMODE
msr cpsr_cxsf,r1 ;SVCMode
ldr sp,=SVCStack
;NOTE:USER mode is not initialized.
; If you want to use the USER mode, the USER mode stack should be initialized.
mov pc,lr ;The LR register may be not valid for the mode changes.
LTORG
;*****************************************************************
;* Memory configuration should be optimized for best performance *
;* The following parameter is not optimized. *
;*****************************************************************
G0_TCOS EQU 0
G0_TACS EQU 0
G0_TCOH EQU 0
G0_TACC EQU (5) ;6 cycles
G0_BA EQU (0x0>>20)
G0_EA EQU ((0x3ffff>>20)+1)
G1_TCOS EQU 0
G1_TACS EQU 0
G1_TCOH EQU 0
G1_TACC EQU (5) ;6 cycles
G1_BA EQU (0x800000>>20)
G1_EA EQU ((0x83ffff>>20)+1)
G2_TCOS EQU 0
G2_TACS EQU 0
G2_TCOH EQU 0
G2_TACC EQU 2 ;3 cycles
G2_BA EQU (0xc00000>>20)
G2_EA EQU ((0xc3ffff>>20)+1)
SMRDATA DATA
DCD (G0_TCOS<<2)+(G0_TACS<<5)+(G0_TCOH<<8)+(G0_TACC<<11)+(G0_BA<<16)+(G0_EA<<24)
DCD (G1_TCOS<<2)+(G1_TACS<<5)+(G1_TCOH<<8)+(G1_TACC<<11)+(G1_BA<<16)+(G1_EA<<24)
DCD (G2_TCOS<<2)+(G2_TACS<<5)+(G2_TCOH<<8)+(G2_TACC<<11)+(G2_BA<<16)+(G2_EA<<24)
ALIGN
AREA RamData, DATA, READWRITE
_4STACKS_SIZE EQU (_UNDEF_STACK_SIZE+_ABORT_STACK_SIZE+_IRQ_STACK_SIZE+_FIQ_STACK_SIZE)
^ (_ISR_STARTADDRESS-_4STACKS_SIZE)
SVCStack # _UNDEF_STACK_SIZE
UndefStack # _ABORT_STACK_SIZE
AbortStack # _IRQ_STACK_SIZE
IRQStack # _FIQ_STACK_SIZE
FIQStack # 0
^ _ISR_STARTADDRESS
HandleReset # 4
HandleUndef # 4
HandleSWI # 4
HandlePabort # 4
HandleDabort # 4
HandleReserved # 4
HandleIRQ # 4
HandleFIQ # 4
;Don't use the label 'IntVectorTable',
;because armasm.exe cann't recognize this label correctly.
;the value is different with an address you think it may be.
;IntVectorTable
HandleURXD # 4
HandleUTXD # 4
HandleUERR # 4
HandleT0OVF # 4
HandleT0MC # 4
HandleT1OVF # 4
HandleT1MC # 4
HandleT2OVF # 4
HandleT2MC # 4
HandleT3OVF # 4
HandleT3MC # 4
HandleT4OVF # 4
HandleT4MC # 4
HandleT5OVF # 4
HandleT5MC # 4
HandleBT # 4
HandleEINT0 # 4
HandleEINT1 # 4
HandleEINT2 # 4
END
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