nand_base.c

this is for nand controller

//NAND controller driver

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/jiffies.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/byteorder/generic.h>
#include <linux/reboot.h>
#include <linux/vmalloc.h>

#include <asm/io.h>
#include <asm/bug.h>
#include <asm/system.h> //
#include <asm/delay.h>

#ifdef MTD_LARGE
#include <linux/mtd/mtd64.h>
#endif

//#include "bbm.h"

#include "nand_priv.h"

#define PRINTK(...)
//#define PRINTK printk
static char NandMsg[1024];

#define my_be32_to_cpu(x) be32_to_cpu(x)

#ifdef CONFIG_MIPS_B0
	#define PLATFORM_IOFLUSH_WAR()	__sync()
#else
	#define PLATFORM_IOFLUSH_WAR()	
#endif

#ifdef CONFIG_MTD_NAND_EDU

#include "edu.h"

// Prototypes
#include "eduproto.h"
#endif // #ifdef CONFIG_MTD_NAND_EDU

int gdebug=0;

// Whether we should clear the BBT to fix a previous error.
/* This will eventually be on the command line, to allow a user to 
 * clean the flash
 */
extern int gClearBBT;

/* Number of NAND chips, only applicable to v1.0+ NAND controller */
extern int gNumNand;

/* The Chip Select [0..7] for the NAND chips from gNumNand above, only applicable to v1.0+ NAND controller */
extern int* gNandCS;

#define DRIVER_NAME	"nand"

#define HW_AUTOOOB_LAYOUT_SIZE		32 /* should be enough */

#define NAND_CORRECTABLE_ECC_ERROR		(1)
#define NAND_SUCCESS					(0)
#define NAND_UNCORRECTABLE_ECC_ERROR	(-1)
#define NAND_FLASH_STATUS_ERROR			(-2)
#define NAND_TIMED_OUT					(-3)

#ifdef CONFIG_MTD_NAND_EDU
#define EDU_CORRECTABLE_ECC_ERROR        (4)
#define EDU_UNCORRECTABLE_ECC_ERROR      (-4)

uint32_t EDU_ldw;
#endif // #ifdef CONFIG_MTD_NAND_EDU

#ifdef CONFIG_MTD_NAND_CORRECTABLE_ERR_HANDLING
/* Avoid infinite recursion between nand_refresh_blk() and nand_read_ecc() */
static atomic_t inrefresh = ATOMIC_INIT(0); 
static int nand_refresh_blk(struct mtd_info *, loff_t);
static int nand_erase_nolock(struct mtd_info *, struct erase_info *, int);
#endif


/*
 * MTD structure for  NAND
 */
//static struct mtd_info *nand_mtd = NULL;


typedef struct nand_chip_Id {
    	uint8 mafId, chipId;
	const char* chipIdStr;
	uint32 options;
	uint32 timing1, timing2; // Specify a non-zero value to override the default timings.
	unsigned int ctrlVersion; // Required controller version if different than 0
} nand_chip_Id;

/*
 * List of supported chip
 */
static nand_chip_Id nand_chips[] = {
	{	/* 0 */
		.chipId = SAMSUNG_K9F1G08U0A,
		.mafId = FLASHTYPE_SAMSUNG,
		.chipIdStr = "Samsung K9F1G08U0A",
		.options = NAND_USE_FLASH_BBT, 		/* Use BBT on flash */
				//| NAND_COMPLEX_OOB_WRITE	/* Write data together with OOB for write_oob */
		.timing1 = 0, //00070000,
		.timing2 = 0,
		.ctrlVersion = 0, /* THT Verified on data-sheet 7/10/08: Allows 4 on main and 4 on OOB */
	},

	{	/* 1 */
		.chipId = ST_NAND512W3A,
		.mafId = FLASHTYPE_ST,
		.chipIdStr = "ST ST_NAND512W3A",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, //0x6474555f, 
		.timing2 = 0, //0x00000fc7,
		.ctrlVersion = 0,
	},
	{	/* 2 */
		.chipId = ST_NAND256W3A,
		.mafId = FLASHTYPE_ST,
		.chipIdStr = "ST ST_NAND256W3A",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, //0x6474555f, 
		.timing2 = 0, //0x00000fc7,
		.ctrlVersion = 0,
	},
#if 0 // EOL
	{	/* 4 */
		.chipId = HYNIX_HY27UF081G2M,
		.mafId = FLASHTYPE_HYNIX,
		.chipIdStr = "HYNIX HY27UF081G2M",
		.options = NAND_USE_FLASH_BBT 
			,
	},
#endif
	/* This is the new version of HYNIX_HY27UF081G2M which is EOL.
	 * Both use the same DevID
	 */
	{	/* 3 */
		.chipId = HYNIX_HY27UF081G2A,
		.mafId = FLASHTYPE_HYNIX,
		.chipIdStr = "Hynix HY27UF081G2A",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = 0,
	},

	{	/* 4 */
		.chipId = MICRON_MT29F2G08AAB,
		.mafId = FLASHTYPE_MICRON,
		.chipIdStr = "MICRON_MT29F2G08AAB",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = 0,
	},
/* This is just the 16 bit version of the above?
	{
		.chipId = MICRON_MT29F2G16AAB,
		.mafId = FLASHTYPE_MICRON,
		.chipIdStr = "MICRON_MT29F2G16AAB",
		.options = NAND_USE_FLASH_BBT 
			,
	}
*/

	{	/* 5 */
		.chipId = SAMSUNG_K9F2G08U0A,
		.mafId = FLASHTYPE_SAMSUNG,
		.chipIdStr = "Samsung K9F2G08U0A",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = CONFIG_MTD_NAND_VERS_2_2,
	},

	{	/* 6 */
		.chipId = SAMSUNG_K9K8G08U0A,
		.mafId = FLASHTYPE_SAMSUNG,
		.chipIdStr = "Samsung K9K8G08U0A",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = CONFIG_MTD_NAND_VERS_2_2,
	},


	{	/* 7 */
		.chipId = HYNIX_HY27UF082G2A,
		.mafId = FLASHTYPE_HYNIX,
		.chipIdStr = "Hynix HY27UF082G2A",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = 0,
	},



	{	/* 8 */
		.chipId = HYNIX_HY27UF084G2M,
		.mafId = FLASHTYPE_HYNIX,
		.chipIdStr = "Hynix HY27UF084G2M",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = 0,
	},

	{	/* 9 */
		.chipId = SPANSION_S30ML512P_08,
		.mafId = FLASHTYPE_SPANSION,
		.chipIdStr = "SPANSION S30ML512P_08",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = 0,
	},

	{	/* 10 */
		.chipId = SPANSION_S30ML512P_16,
		.mafId = FLASHTYPE_SPANSION,
		.chipIdStr = "SPANSION S30ML512P_16",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = 0,
	},

	{	/* 11 */
		.chipId = SPANSION_S30ML256P_08,
		.mafId = FLASHTYPE_SPANSION,
		.chipIdStr = "SPANSION S30ML256P_08",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = 0,
	},

	{	/* 12 */
		.chipId = SPANSION_S30ML256P_16,
		.mafId = FLASHTYPE_SPANSION,
		.chipIdStr = "SPANSION S30ML256P_16",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = 0,
	},

	{	/* 13 */
		.chipId = SPANSION_S30ML128P_08,
		.mafId = FLASHTYPE_SPANSION,
		.chipIdStr = "SPANSION S30ML128P_08",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = 0,
	},

	{	/* 14 */
		.chipId = SPANSION_S30ML128P_16,
		.mafId = FLASHTYPE_SPANSION,
		.chipIdStr = "SPANSION S30ML128P_16",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = 0,
	},

	{	/* 15 */
		.chipId = SPANSION_S30ML01GP_08,
		.mafId = FLASHTYPE_SPANSION,
		.chipIdStr = "SPANSION_S30ML01GP_08",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = 0,
	},

	{	/* 16 */
		.chipId = SPANSION_S30ML01GP_16,
		.mafId = FLASHTYPE_SPANSION,
		.chipIdStr = "SPANSION_S30ML01GP_16",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = 0,
	},

	{	/* 17 */
		.chipId = SPANSION_S30ML02GP_08,
		.mafId = FLASHTYPE_SPANSION,
		.chipIdStr = "SPANSION_S30ML02GP_08",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = 0,
	},

	{	/* 18 */
		.chipId = SPANSION_S30ML02GP_16,
		.mafId = FLASHTYPE_SPANSION,
		.chipIdStr = "SPANSION_S30ML02GP_16",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = 0,
	},

	{	/* 19 */
		.chipId = SPANSION_S30ML04GP_08,
		.mafId = FLASHTYPE_SPANSION,
		.chipIdStr = "SPANSION_S30ML04GP_08",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = 0,
	},

	{	/* 20 */
		.chipId = SPANSION_S30ML04GP_16,
		.mafId = FLASHTYPE_SPANSION,
		.chipIdStr = "SPANSION_S30ML04GP_16",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = 0,
	},

	{	/* 21 */
		.chipId = ST_NAND128W3A,
		.mafId = FLASHTYPE_ST,
		.chipIdStr = "ST NAND128W3A",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = 0,
	},

	/* The following 6 ST chips only allow 4 writes per page, and requires version2.2 (5) of the controller or later */
	{	/* 22 */
		.chipId = ST_NAND01GW3B,
		.mafId = FLASHTYPE_ST,
		.chipIdStr = "ST NAND01GW3B2B",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = CONFIG_MTD_NAND_VERS_2_2,
	},

	{	/* 23 */ 
		.chipId = ST_NAND01GR3B,
		.mafId = FLASHTYPE_ST,
		.chipIdStr = "ST NAND01GR3B2B",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = CONFIG_MTD_NAND_VERS_2_2,
	},

	{	/* 24 */ 
		.chipId = ST_NAND02GR3B,
		.mafId = FLASHTYPE_ST,
		.chipIdStr = "ST NAND02GR3B2C",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = CONFIG_MTD_NAND_VERS_2_2,
	},
	{	/* 25 */ 
		.chipId = ST_NAND02GW3B,
		.mafId = FLASHTYPE_ST,
		.chipIdStr = "ST NAND02GW3B2C",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = CONFIG_MTD_NAND_VERS_2_2,
	},
	
	{	/* 26 */ 
		.chipId = ST_NAND04GW3B,
		.mafId = FLASHTYPE_ST,
		.chipIdStr = "ST NAND04GW3B2B",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = CONFIG_MTD_NAND_VERS_2_2,
	},
	{	/* 27 */ 
		.chipId = ST_NAND08GW3B,
		.mafId = FLASHTYPE_ST,
		.chipIdStr = "ST NAND08GW3B2A",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
		.ctrlVersion = CONFIG_MTD_NAND_VERS_2_2,
	},
		
	{	/* 28 */
		.chipId = SAMSUNG_K9LBG08U0M,
		.mafId = FLASHTYPE_SAMSUNG,
		.chipIdStr = "Samsung K9LBG08U0M ",
		.options = NAND_USE_FLASH_BBT, 		/* Use BBT on flash */
				//| NAND_COMPLEX_OOB_WRITE	/* Write data together with OOB for write_oob */
		.timing1 = 0, //00070000,
		.timing2 = 0,
		.ctrlVersion = 0, /* THT Verified on data-sheet 7/10/08: Allows 4 on main and 4 on OOB */
	},
		
	{	/* LAST DUMMY ENTRY */
		.chipId = 0,
		.mafId = 0,
		.chipIdStr = "UNSUPPORTED NAND CHIP",
		.options = NAND_USE_FLASH_BBT,
		.timing1 = 0, .timing2 = 0,
	}
};

// Max chip account for the last dummy entry
#define NAND_MAX_CHIPS (ARRAY_SIZE(nand_chips) - 1)

#include <mtd/nand_oob.h> /* NAND controller defined OOB */

static const unsigned char ffchars[] = {
	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 16 */
	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 32 */
	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 48 */
	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 64 */
};

static unsigned char eccmask[128]; // Will be initialized during probe


static uint32_t nand_ctrl_read(uint32_t nandCtrlReg) 
{
	volatile unsigned long* pReg = (volatile unsigned long*) (NAND_CTRL_REGS 
		+ nandCtrlReg - BCHP_NAND_REVISION);

	if (nandCtrlReg < BCHP_NAND_REVISION || nandCtrlReg > BCHP_NAND_BLK_WR_PROTECT ||
		(nandCtrlReg & 0x3) != 0) {
		printk(KERN_ERR "nand_ctrl_read: Invalid register value %08x\n", nandCtrlReg);
	}
if (gdebug > 3) printk("%s: CMDREG=%08x val=%08x\n", __FUNCTION__, (unsigned int) nandCtrlReg, (unsigned int)*pReg);
	return (uint32_t) (*pReg);
}


static void nand_ctrl_write(uint32_t nandCtrlReg, uint32_t val) 
{
	volatile unsigned long* pReg = (volatile unsigned long*) (NAND_CTRL_REGS 
		+ nandCtrlReg - BCHP_NAND_REVISION);

	if (nandCtrlReg < BCHP_NAND_REVISION || nandCtrlReg > BCHP_NAND_BLK_WR_PROTECT ||
		(nandCtrlReg & 0x3) != 0) {
		printk(KERN_ERR "nand_ctrl_read: Invalid register value %08x\n", nandCtrlReg);
	}
	*pReg = (volatile unsigned long) (val);
if (gdebug > 3) printk("%s: CMDREG=%08x val=%08x\n", __FUNCTION__, nandCtrlReg, val);
}


/*
 * chip:  NAND handle
 * offset: offset from start of mtd, not necessarily the same as offset from chip.
 * cmdEndAddr: 1 for CMD_END_ADDRESS, 0 for CMD_ADDRESS
 */
static void nand_ctrl_writeAddr(struct nand_chip* chip, L_OFF_T offset, int cmdEndAddr) 
{