i2s.h

i2s usb audio demo lpc2138

#ifndef I2S_H_FILE
#define I2S_H_FILE 1

/*MPMC(EMC) registers*/
#define STATIC_MEM0_BASE        0x80000000
#define STATIC_MEM1_BASE        0x81000000
#define STATIC_MEM2_BASE        0x82000000
#define STATIC_MEM3_BASE        0x83000000

#define DYNAMIC_MEM0_BASE		0xA0000000
#define DYNAMIC_MEM1_BASE		0xB0000000
#define DYNAMIC_MEM2_BASE		0xC0000000
#define DYNAMIC_MEM3_BASE		0xD0000000

enum e_word_width 
{
  I2S_8BIT  = 0x0,
  I2S_16BIT = 0x1,
  I2S_32BIT = 0x3
};

enum e_ws_sel
{
  I2S_MASTER  = 0,
  I2S_SLAVE = 1 
};

enum e_mono
{
  I2S_STEREO = 0,
  I2S_MONO   = 1
};

enum e_halfword
{
  I2S_HALFWORD8 = 8-1,
  I2S_HALFWORD16 = 16-1,
  I2S_HALFWORD20 = 20-1,
  I2S_HALFWORD32 = 32-1
};

#define I2STXFIFO_FULL 8
#define I2SRXFIFO_EMPTY 0

typedef union 
{
  struct 
  {
    int word_width   : 2;   // [1:0]
    int mono         : 1;   // [2]
    int stop         : 1;   // [3]
    int reset        : 1;   // [4]
    int ws_sel       : 1;   // [5]
    int ws_halfperiod: 9;   // [14:6]
    int mute         : 1;   // [15]
    int bit31_16     : 16;  // [31:16]
  } bit_field;
  
  unsigned int value;
  
} t_i2s_control;

typedef union 
{
  struct 
  {
    int rx_dma_enable: 1;   // [0]
    int tx_dma_enable: 1;   // [1]
    int bit7_2       : 6;   // [7:2]
    int rx_depth_dma : 8;   // [15:8]
    int tx_depth_dma : 8;   // [23:16]
    int bit31_24     : 8;   // [31:24]
  } bit_field;
  
  unsigned int value;
  
} t_i2s_dma;

typedef union 
{
  struct 
  {
    int rx_irq_enable: 1;   // [0]
    int tx_irq_enable: 1;   // [1]
    int bit7_2       : 6;   // [7:2]
    int rx_depth_irq : 8;   // [15:8]
    int tx_depth_irq : 8;   // [23:16]
    int bit31_24     : 8;   // [31:24]
  } bit_field;
  
  unsigned int value;
  
} t_i2s_irq;

typedef union 
{
  struct 
  {
    int irq_umask    : 1;   // [0]
    int dmareq1_umask: 1;   // [1]
    int dmareq2_umask: 1;   // [2]
    int bit7_3       : 5;   // [7:3]
    int rx_level     : 8;   // [15:8]
    int tx_level     : 8;   // [23:16]
    int bit31_24     : 8;   // [31:24]
  } bit_field;
  
  unsigned int value;
  
} t_i2s_state;


#define I2SDAI_REG   (*(volatile t_i2s_control *)&(I2S_DAI))
#define I2SDAO_REG   (*(volatile t_i2s_control *)&(I2S_DAO))
#define I2SSTATE_REG (*(volatile t_i2s_state *)  &(I2S_STATE))
#define I2SDMA1_REG  (*(volatile t_i2s_dma *)    &(I2S_DMA1))
#define I2SDMA2_REG  (*(volatile t_i2s_dma *)    &(I2S_DMA2))
#define I2SIRQ_REG   (*(volatile t_i2s_irq *)    &(I2S_IRQ))

typedef union{
  struct{
    DWORD TransferSize  :12; //[11:0]
    DWORD SBSize        :3;  //[14:12]
    DWORD DBSize        :3;  //[17:15]
    DWORD SWidth        :3;  //[20:18] 
    DWORD DWidth        :3;  //[23:21]
    DWORD Reserved      :2;  //[25:24]
    DWORD SI            :1;  //[26]
    DWORD DI            :1;  //[27]
    DWORD Prot          :3;  //[30:28]
    DWORD I             :1;  //[31]
  } bit_field;

  DWORD four_byte;

} t_DMACCxControl;

typedef struct
{
  DWORD SrcAddr;
  DWORD DestAddr;
  DWORD LLI;
  DWORD Control;
} t_LLI;

extern int i2s_init(void);

extern int i2s_config_rxrate(unsigned int bitrate, unsigned int pclk_i2s_freq);
extern int i2s_config_txrate(unsigned int bitrate, unsigned int pclk_i2s_freq);

extern void i2s_set_tx_depth_irq(int depth);
extern void i2s_set_rx_depth_irq(int depth);

extern void i2s_enable_tx_irq(int flag);
extern void i2s_enable_rx_irq(int flag);

extern void i2s_enable_irq_in_vic(int flag);

extern __irq void i2s_irq(void);
extern void i2s_irq_service(void);

extern void i2s_config_dai(unsigned int wordwidth, unsigned int mono, 
                    unsigned int ws_sel, unsigned int ws_halfperiod);
extern void i2s_config_dao(unsigned int wordwidth, unsigned int mono, 
                    unsigned int ws_sel, unsigned int ws_halfperiod);

extern void i2s_enable_dai(int flag);
extern void i2s_enable_dao(int flag);
extern void i2s_enable_daio(int flag);	/* disable : reset clear tx & rx fifo and stop */

extern void i2s_mute_dao(int flag);

		  
#endif