pcielink.txt

PCI-Express Lane Test Utility. Validates negotiated lane capability registers, returns error codes,

 Examples for PCIELINK.EXE  PCI EXPRESS LINK CAPABILITY TEST V2.0

 Created by: Jeff Fabrizio, QLogic Corporation FVT Production Test

  VendorID QLOGIC          4215  0x1077 
           HP              4156  0x103C 
           SUN              284  0x011C 
           NEC             4147  0x1033 
           PLX             4187  0x10B5 
  DeviceID ISP2432         9266  0x2432 
           ISP2532         9522  0x2532 
           NEC UPD720403    335  0x014F 
           PLX8516/1517   34070  0x4277 

 The /e /f /g options require three values separated by a semicolon. These
 options are not required for QLogic ISP devices but are required for non-
 QLogic devices such as the NEC or PLX PCI bridge devices.  The design spec
 for any device is required to obtain the PCI register offset values for:
  PCI Maximum Lane Width
  PCI Negotiated Lane Width
  PCI Negotiated Lane Speed

  example:
  /eRegMLW;msb;lsb
  /fRegNLW;msb;lsb
  /gRegNLS;msb;lsb

   RegMLW = Register Maximum Link Width
   RegNLW = Register Negotiated Link Width
   RegNLS = Register Negotiated Link Speed
      msb = most significant bit offset
      lsb = least significant bit offset

*QLogic 2432  (Default device)
PCIELINK /v /h /i4215 /a9266 /s4215 /m4 /n4 /l1 /e88;9;4 /f94;9;4 /g94;3;0
*QLogic 5432
4215;21554
*QLogic 6432
4215;25650
*QLogic 7432
4215;29746
*QLogic 8432
4215;33842
*QLogic 2532
4215;9522;
*QLogic 6220
4215;25120
*QLogic 7220
4215;29216
*QLogic 8000
4215;32768;88;9;4;94;9;4;94;3;0
*QLogic 8001
4215;32769;88;9;4;94;9;4;94;3;0
*NEC uPD720403 Port 0 PCI Motherboard
PCIELINK /v /h /i4147 /a335 /m8 /n8 /s0 /e108;9;4 /f114;9;4 /g114;3;0
*NEC uPD720403 Port 1 PCI ISP 0
PCIELINK /v /h /i4147 /a336 /m8 /n8 /s0 /e108;9;4 /f114;9;4 /g114;3;0
*NEC uPD720403 Port 2 PCI ISP 1
PCIELINK /v /h /i4147 /a337 /m8 /n8 /s0 /e108;9;4 /f114;9;4 /g114;3;0
*NEC uPD720403 Port 3 unused
PCIELINK /v /h /i4147 /a338 /m8 /n8 /s0 /e108;9;4 /f114;9;4 /g114;3;0
*PLX 8516/8517
PCIELINK /v /h /i4277 /a34070 /s0 /m8 /n8 /e116;9;4 /f122;9;4 /g122;3;0

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