4510addr.h

it is a sample code for s3c2410 board.

;UART control registers
;============================================================================================*/
#define ULCON0          (*(volatile unsigned *)0x03FFD000)      //0x00          ; UART channel 0 line control register
#define UCON0           (*(volatile unsigned *)0x03FFD004)      //0x00          ; UART channel 0 control register
#define USTAT0          (*(volatile unsigned *)0x03FFD008)      //0xC0          ; UART channel 0 status register
#define UTXBUF0         (*(volatile unsigned *)0x03FFD00c)      //Undefined     ; UART channel 0 transmit holding register
#define URXBUF0         (*(volatile unsigned *)0x03FFD010)      //Undefined     ; UART channel 0 receive buffer register
#define UBRDIV0         (*(volatile unsigned *)0x03FFD014)      //0x00          ; Baud rate divisor register 0

#define ULCON1          (*(volatile unsigned *)0x03FFe000)      //0x00          ; UART channel 1 line control register
#define UCON1           (*(volatile unsigned *)0x03FFe004)      //0x00          ; UART channel 1 control register
#define USTAT1          (*(volatile unsigned *)0x03FFe008)      //0xC0          ; UART channel 1 status register
#define UTXBUF1         (*(volatile unsigned *)0x03FFe00c)      //Undefined     ; UART channel 1 transmit holding register
#define URXBUF1         (*(volatile unsigned *)0x03FFe010)      //Undefined     ; UART channel 1 receive buffer register
#define UBRDIV1         (*(volatile unsigned *)0x03FFe014)      //0x00          ; Baud rate divisor register 1

#define WrUTXH0(c)      UTXBUF0 = (unsigned char)(c)
#define RdURXH0()       URXBUF0

/*============================================================================================
;Timers control registers
;============================================================================================*/
#define TMOD            (*(volatile unsigned *)0x03FF6000)     // 0x00000000    ; Timer mode register
#define TDATA0          (*(volatile unsigned *)0x03FF6004)     // 0x00000000    ; Timer 0 data register
#define TCNT0           (*(volatile unsigned *)0x03FF600C)     // 0xFFFFFFFF    ; Timer 0 count register
#define TDATA1          (*(volatile unsigned *)0x03FF6008)     // 0x00000000    ; Timer 1 data register
#define TCNT1           (*(volatile unsigned *)0x03FF6010)     // 0xFFFFFFFF    ; Timer 1 count register


// ISR
extern unsigned pISR_RESET ;
extern unsigned pISR_UNDEF;
extern unsigned pISR_SWI;
extern unsigned pISR_PABORT;
extern unsigned pISR_DABORT;
extern unsigned pISR_RESERVED;
extern unsigned pISR_IRQ;
extern unsigned pISR_FIQ;

extern unsigned pISR_EXT0;
extern unsigned pISR_EXT1;
extern unsigned pISR_EXT2;
extern unsigned pISR_EXT3;
extern unsigned pISR_U0TINT;
extern unsigned pISR_U0RERR;
extern unsigned pISR_U1TINT;
extern unsigned pISR_U1RERR;
extern unsigned pISR_GDMA0;
extern unsigned pISR_GDMA1;
extern unsigned pISR_TIMER0;
extern unsigned pISR_TIMER1;
extern unsigned pISR_HDLCTXA;
extern unsigned pISR_HDLCRXA;
extern unsigned pISR_HDLCTXB;
extern unsigned pISR_HDLCRXB;
extern unsigned pISR_ECBDMATx;
extern unsigned pISR_ECBDMARx;
extern unsigned pISR_ECMACTx;
extern unsigned pISR_ECMACRx;
extern unsigned pISR_i2cbus;


// PENDING BIT
#define EXT0            0  /* external interrupt 0             */
#define EXT1            1  /* external interrupt 1             */
#define EXT2            2  /* external interrupt 2             */
#define EXT3            3  /* external interrupt 3             */
#define U0TINT          4  /* uart0 transmit interrupt         */
#define U0RERR          5  /* uart0 receive & error interrupt  */
#define U1TINT          6  /* uart1 transmit interrupt         */
#define U1RERR          7  /* uart1 receive & error interrupt  */
#define GDMA0           8  /* GDMA channel 0 interrupt         */
#define GDMA1           9  /* GDMA channel 1 interrupt         */
#define TIMER0          10  /* timer 0 interrupt                */
#define TIMER1          11  /* timer 1 interrupt                */
#define HDLCTXA         12  /* HDLC channel A TX interrupt      */
#define HDLCRXA         13  /* HDLC channel A Rx interrupt      */
#define HDLCTXB         14  /* HDLC channel B TX interrupt      */
#define HDLCRXB         15  /* HDLC channel B Rx interrupt      */
#define ECBDMATx        16  /* Eternet controller BDMA Tx intrrupt*/
#define ECBDMARx        17  /* Eternet controller BDMA Rx intrrupt*/
#define ECMACTx         18  /* Eternet controller BDMA Tx intrrupt*/
#define ECMACRx         19  /* Eternet controller BDMA Rx intrrupt*/
#define i2cbus          20  /* i2 C-bus interrupt                 */

#define BIT_EXT0        (0x1)
#define BIT_EXT1        (0x1<<1)
#define BIT_EXT2        (0x1<<2)
#define BIT_EXT3        (0x1<<3)
#define BIT_U0TINT      (0x1<<4)
#define BIT_U0RERR      (0x1<<5)
#define BIT_U1TINT      (0x1<<6)
#define BIT_U1RERR      (0x1<<7)
#define BIT_GDMA0       (0x1<<8)
#define BIT_GDMA1       (0x1<<9)
#define BIT_TIMER0      (0x1<<10)
#define BIT_TIMER1      (0x1<<11)
#define BIT_HDLCTXA     (0x1<<12)
#define BIT_HDLCRXA     (0x1<<13)
#define BIT_HDLCTXB     (0x1<<14)
#define BIT_HDLCRXB     (0x1<<15)
#define BIT_ECBDMATx    (0x1<<16)
#define BIT_ECBDMARx    (0x1<<17)
#define BIT_ECMACTx     (0x1<<18)
#define BIT_ECMACRx     (0x1<<19)
#define BIT_i2cbus      (0x1<<20)
#define BIT_GMASK       (0x1<<21)
#define BIT_ALLMSK      (0xffffffff)


#define ClearPending(bit) {             \
                        INTPND = (bit); \
                        }

#define EnableInterrupt(x)       INTMSK &= (~x);
#define DisableInterrupt(x)      INTMSK |= (x);



/*============================================================================================
;Peripheral control registers
;============================================================================================*/
#define ECS0_BASE 		0x03F00000

#define CF_TASK_BASE 	(ECS0_BASE+0x0000)	/* CF_nCS0 */
#define CF_STATUS_BASE	(ECS0_BASE+0x0200)	/* CF_nCS1 : not used */

#define ATA_BYTDATREG   (*(unsigned short *)(CF_TASK_BASE+0x0000)) /* DATA read/write */
#define ATA_ERRFEAREG   (*(unsigned short *)(CF_TASK_BASE+0x0002)) /* read error/write feature */
#define ATA_SECTCOUNT   (*(unsigned short *)(CF_TASK_BASE+0x0004)) /* sector count */
#define ATA_SECTORNO    (*(unsigned short *)(CF_TASK_BASE+0x0006)) /* sector number */
#define ATA_CYLINDLOW   (*(unsigned short *)(CF_TASK_BASE+0x0008)) /* cylinder low */
#define ATA_CYLINDHI    (*(unsigned short *)(CF_TASK_BASE+0x000A)) /* cylinder high */
#define ATA_SCARDHEAD   (*(unsigned short *)(CF_TASK_BASE+0x000C)) /* select card/head */
#define ATA_STATCOMMD   (*(unsigned short *)(CF_TASK_BASE+0x000E)) /* read status/write command */

#define USB_DATA 		(*(unsigned short *)(ECS0_BASE+0x0400))
#define USB_CMD 		(*(unsigned short *)(ECS0_BASE+0x0402))
#define CCM_DATA 		(*(unsigned short *)(ECS0_BASE+0x0600))
#define LCD_CMD 		(*(unsigned short *)(ECS0_BASE+0x0800))
#define LCD_DATA 		(*(unsigned short *)(ECS0_BASE+0x0802))
#define CODEC_DATA 		(*(unsigned short *)(ECS0_BASE+0x0A00))
#define IO_REG0			(*(unsigned short *)(ECS0_BASE+0x0C00))
#define IO_REG1 		(*(unsigned short *)(ECS0_BASE+0x0C02))	
#define IO_REG2 		(*(unsigned short *)(ECS0_BASE+0x0C04))	
#define CPLD_CTRL 		(*(unsigned short *)(ECS0_BASE+0x0E00))	/* Write */
						//00	: IO_nRST
						//01	: AIC_ON
						//02	: EXPTM1
						//03	: EXPTM2
						//04	: FPGA_nPGM
						//05	: FPGA_CCLK
						//06	: IRQ3_SEL
						//07	: DMA_SEL
#define CPLD_STATUS		(*(unsigned short *)(ECS0_BASE+0x0E00))	/* Read */
						//00 	: EE_DO
						//01 	: USB_nEOT
						//02 	: USB_ON
						//03 	: NA
						//04 	: CCD_nRDY
						//05-15 : 0


#ifdef __cplusplus
}
#endif
#define inl(addr)        (addr)
#define outl(data, addr) ((addr) = (data))

#endif