4510addr.a

it is a sample code for s3c2410 board.

;==============================================================================
;  File Name : 4510addr.a
;  Function  : S3C4510 Define Address Register
;  Program   : 
;  Date      : February 24, 2003
;  Version   : 0.0
;  History
;    0.0 : Programming start (February 24,2003) -> SOP
; =============================================================================


;=========================================================================================================
;System Manager control 
;=========================================================================================================
SYSCON      	DEFINE  0x03FF0000	;0x07FFFF91	;System configuration register		
CLKCON	   	DEFINE	0x03FF3000	;0x00000000	;Clock control register			
EXTACON0  	DEFINE	0x03FF3008	;0x00000000	;External I/O timing register 1		
EXTACON1  	DEFINE	0x03FF300C 	;0x00000000	;External I/O timing register 2		
EXTDBWTH  	DEFINE	0x03FF3010 	;0x00000000	;Data bus width of each bank		
ROMCON0   	DEFINE	0x03FF3014 	;0x20000060	;ROM/SRAM/Flash bank 0 control register	
ROMCON1   	DEFINE	0x03FF3018 	;0x00000060	;ROM/SRAM/Flash bank 1 control register	
ROMCON2   	DEFINE	0x03FF301C 	;0x00000060	;ROM/SRAM/Flash bank 2 control register	
ROMCON3   	DEFINE	0x03FF3020 	;0x00000060	;ROM/SRAM/Flash bank 3 control register	
ROMCON4   	DEFINE	0x03FF3024 	;0x00000060	;ROM/SRAM/Flash bank 4 control register	
ROMCON5   	DEFINE	0x03FF3028 	;0x00000060	;ROM/SRAM/Flash bank 5 control register	
DRAMCON0  	DEFINE	0x03FF302C 	;0x00000000	;DRAM bank 0 control register		
DRAMCON1  	DEFINE	0x03FF3030 	;0x00000000	;DRAM bank 0 control register		
DRAMCON2  	DEFINE	0x03FF3034 	;0x00000000	;DRAM bank 0 control register		
DRAMCON3  	DEFINE	0x03FF3038 	;0x00000000	;DRAM bank 0 control register		
REFEXTCON 	DEFINE	0x03FF303C 	;0x83FD0000	;Refresh and external I/O control register 


;===========================================================================================================
;Ethernet(BDMA) registers
;===========================================================================================================
BDMATXCON  	DEFINE	0x03FF9000	;0x00000000	; Buffered DMA receive control register		
BDMARXCON   	DEFINE	0x03FF9004      ;0x00000000	; Buffered DMA transmit control register
BDMATXPTR   	DEFINE	0x03FF9008      ;0xFFFFFFFF	; Transmit trame descriptor start address
BDMARXPTR   	DEFINE	0x03FF900C      ;0xFFFFFFFF	; Receive frame descriptor start address
BDMARXLSZ   	DEFINE	0x03FF9010      ;Undefined	; Receive frame maximum size
BDMASTAT    	DEFINE	0x03FF9014      ;0x00000000	; Buffered DMA status


;===========================================================================================================
;Ethernet(MAC) registers
;===========================================================================================================
MACON       	DEFINE	0x03FFA000      ;0x00000000	; Ethernet MAC control register	
CAMCON      	DEFINE	0x03FFA004      ;0x00000000	; CAM control register	
MACTXCON    	DEFINE	0x03FFA008      ;0x00000000	; MAC transmit control register
MACTXSTAT   	DEFINE	0x03FFA00C      ;0x00000000	; MAC transmit status register
MACRXCON    	DEFINE	0x03FFA010      ;0x00000000	; MAC receive control register
MACRXSTAT   	DEFINE	0x03FFA014      ;0x00000000	; MAC receive status register
STADATA     	DEFINE	0x03FFA018      ;0x00000000	; Station management data
STACON      	DEFINE	0x03FFA01C      ;0x00006000	; Station management control and address
CAMEN       	DEFINE	0x03FFA028      ;0x00000000	; CAM enable register
EMISSCNT    	DEFINE	0x03FFA03C      ;0x00000000    ; Missed error count
EPZCNT      	DEFINE	0x03FFA040      ;0x00000000    ; Pause count
ERMPZCNT    	DEFINE	0x03FFA044      ;0x00000000    ; Read; Remote pause count
ETXSTAT     	DEFINE	0x03FF9040      ;0x00000000    ; Read; Transmit control frame status


;===========================================================================================================
;HDLC  Channel A Registers
;===========================================================================================================
HMODEA      	DEFINE	0x03FF7000      ;0x00000000	; HDLC mode register
MCONA       	DEFINE	0x03FF7004      ;0x00000000	; HDLC control register
HSTATA      	DEFINE	0x03FF7008      ;0x00000000	; HDLC status register
HINTENA     	DEFINE	0x03FF700C      ;0x00000000	; HDLC interrupt enable register
HTXFIFOCA    	DEFINE	0x03FF7010      ;0x00000000	; TxFIFO frame continue register
HTXFIFOTA     	DEFINE	0x03FF7014      ;0x00000000	; TxFIFO frame terminate register r
HRXFIFOA    	DEFINE	0x03FF7018      ;0x00000000	; THDLC RxFIFO entry register
HBRGTCA     	DEFINE	0x03FF701C      ;0x00000000	; HDLC Baud rate generate time constantr
HPRMBA      	DEFINE	0x03FF7020      ;0x00000000	; HDLC Preamble Constant 0x00000000
HSADR0A     	DEFINE	0x03FF7024      ;0x00000000	; HDLC station address 0
HSADR1A     	DEFINE	0x03FF7028      ;0x00000000	; HDLC station address 1 0x00000000
HSADR2A     	DEFINE	0x03FF702C      ;0x00000000	; HDLC station address 2
HSADR3A     	DEFINE	0x03FF7030      ;0x00000000	; HDLC station address 3
HMASKA      	DEFINE	0x03FF7034      ;0x00000000	; HDLC mask register
HDMATXPTRA  	DEFINE	0x03FF7038      ;0xFFFFFFFF	; DMA Tx buffer descriptor pointer
HDMARXPTRA  	DEFINE	0x03FF703C      ;0xFFFFFFFF	; DMA Rx buffer descriptor pointer
HMFLRA      	DEFINE	0x03FF7040      ;0xXXXX0000	; Maximum frame length register
HRBSRA      	DEFINE	0x03FF7044      ;0xXXXX0000	; DMA receive buffer size register


;===========================================================================================================
;HDLC  Channel B Registersl 
;===========================================================================================================
HMODEB      	DEFINE	0x03FF8000      ;0x00000000	; HDLC mode register
MCONB       	DEFINE	0x03FF8004      ;0x00000000	; HDLC control register
HSTATB      	DEFINE	0x03FF8008      ;0x000104000	; HDLC status register
HINTENB   	DEFINE	0x03FF800C      ;0x00000000	; HDLC interrupt enable register
HTXFIFOCB    	DEFINE	0x03FF8010      ;0x00000000	; TxFIFO frame continue register
HRXFIFOB    	DEFINE	0x03FF8018      ;0x00000000	; HDLC RxFIFO entry register
HBRGTCB     	DEFINE	0x03FF801C      ;0x00000000	; HDLC Baud rate generate time constant
HPRMBB      	DEFINE	0x03FF8020      ;0x00000000	; HDLC Preamble Constant
HSAR0B      	DEFINE	0x03FF8024      ;0x00000000	; HDLC station address 0
HSAR1B      	DEFINE	0x03FF8028      ;0x00000000	; HDLC station address 1
HSAR2B      	DEFINE	0x03FF802C      ;0x00000000	; HDLC station address 2
HSAR3B      	DEFINE	0x03FF8030      ;0x00000000	; HDLC station address 3
HMASKB      	DEFINE	0x03FF8034      ;0x00000000	; HDLC mask register
HDMATXPTRB  	DEFINE	0x03FF8038      ;0xFFFFFFFF	; DMA Tx buffer descriptor pointer
HDMARXPTRB  	DEFINE	0x03FF803C      ;0xFFFFFFFF	; DMA Rx buffer descriptor pointer
HMFLRB      	DEFINE	0x03FF8040      ;0x00000000	; Maximum frame length register
HRBSRB      	DEFINE	0x03FF8044      ;0x00000000	; DMA receive buffer size register

;===========================================================================================================
; I/O control 
; The KS32C50100(4510)has 18 programmable I/O ports.
;===========================================================================================================
IOPMOD		DEFINE	0x03FF5000	;0x00000000 	All Input;I/O port mode register			
IOPCON		DEFINE	0x03FF5004	;0x00000000	;I/O port control registerr		 
IOPDATA		DEFINE	0x03FF5008	;Undefined	;I/O port data register			



;===========================================================================================================
;INTERRUPT 
;===========================================================================================================
INTMOD		DEFINE	0x03FF4000	;0x00000000	;Interrupt mode register 		
INTPND		DEFINE	0x03FF4004	;0x00000000	;Interrupt pending register 		
INTMSK		DEFINE	0x03FF4008	;0x003FFFFF	;Interrupt mask register 		
INTPRI0		DEFINE	0x03FF400C	;0x03020100	;Interrupt priority register 0 		
INTPRI1		DEFINE	0x03FF4010	;0x07060504	;Interrupt priority register 1 		
INTPRI2		DEFINE	0x03FF4014	;0x0B0A0908	;Interrupt priority register 2 		
INTPRI3		DEFINE	0x03FF4018	;0x0F0E0D0C	;Interrupt priority register 3 		
INTPRI4		DEFINE	0x03FF401C	;0x13121110	;Interrupt priority register 4 		
INTPRI5		DEFINE	0x03FF4020	;0x00000014	;Interrupt priority register 5 		
INTOFFSET	DEFINE	0x03FF4024	;0x00000054	;Interrupt offset register 		
INTOSET_FIQ	DEFINE	0x03FF4030	;0x00000054	;FIQ Interrupt offset register 		
INTOSET_IRQ	DEFINE	0x03FF4034	;0x00000054	;IRQ Interrupt offset register 		

;===========================================================================================================
;I2C Bus control registersl 
;===========================================================================================================
IICCON      	DEFINE	0x03FFF000     	;0x00000000	; I2C bus control status register 0x00000054
IICBUF      	DEFINE	0x03FFF004     	;Undefined	; I2C bus shift buffer register
IICPS       	DEFINE	0x03FFF008     	;0x00000000	; I2C bus prescaler register
IICCOUNT    	DEFINE	0x03FFF00C     	;0x00000000	; I2C bus prescaler counter register


;===========================================================================================================
;GDMA control registers 
;===========================================================================================================
GDMACON0    	DEFINE	0x03FFB000     	;0x00000000	; GDMA controller channel 0 control register
GDMACON1    	DEFINE	0x03FFC000    	;0x00000000	; GDMA controller channel 1 control register
GDMASRC0    	DEFINE	0x03FFB004     	;Undefined	; GDMA channel 0 source address register
GDMADST0    	DEFINE	0x03FFB008      ;Undefined	; GDMA channel 0 destination address register
GDMASRC1    	DEFINE	0x03FFC004      ;Undefined	; GDMA channel 1 source address register
GDMADST1    	DEFINE	0x03FFC008      ;Undefined	; GDMA channel 1 destination address register
GDMACNT0    	DEFINE	0x03FFB00C      ;Undefined	; GDMA channel 0 transfer count register
GDMACNT1    	DEFINE	0x03FFC00C      ;Undefined	; GDMA channel 1 transfer count register


;===========================================================================================================
;UART control registers 
;===========================================================================================================
ULCON0		DEFINE	0x03FFD000	;0x00		; UART channel 0 line control register
UCON0		DEFINE	0x03FFD004	;0x00		; UART channel 0 control register
USTAT0		DEFINE	0x03FFD008	;0xC0		; UART channel 0 status register
UTXBUF0		DEFINE	0x03FFD00c	;Undefined	; UART channel 0 transmit holding register
URXBUF0		DEFINE	0x03FFD010	;Undefined 	; UART channel 0 receive buffer register
UBRDIV0		DEFINE	0x03FFD014	;0x00		; Baud rate divisor register 0

ULCON1		DEFINE	0x03FFe000	;0x00		; UART channel 1 line control register
UCON1		DEFINE	0x03FFe004	;0x00		; UART channel 1 control register
USTAT1		DEFINE	0x03FFe008	;0xC0		; UART channel 1 status register
UTXBUF1		DEFINE	0x03FFe00c	;Undefined	; UART channel 1 transmit holding register
URXBUF1		DEFINE	0x03FFe010	;Undefined 	; UART channel 1 receive buffer register
UBRDIV1		DEFINE	0x03FFe014	;0x00		; Baud rate divisor register 1


;===========================================================================================================
;Timers control registers
;======================================================================================================== */
TMOD        	DEFINE	0x03FF6000    	;0x00000000	; Timer mode register
TDATA0      	DEFINE	0x03FF6004     	;0x00000000	; Timer 0 data register
TCNT0       	DEFINE	0x03FF600C     	;0xFFFFFFFF	; Timer 0 count register
TDATA1      	DEFINE	0x03FF6008     	;0x00000000	; Timer 1 data register
TCNT1       	DEFINE	0x03FF6010     	;0xFFFFFFFF	; Timer 1 count register


;=================
; ISR
;=================


;===========================================================================================================
;PENDING BIT
;===========================================================================================================
BIT_EXT0      	DEFINE	(0x1)
BIT_EXT1      	DEFINE	(0x1<<1)  
BIT_EXT2      	DEFINE	(0x1<<2)  
BIT_EXT3      	DEFINE	(0x1<<3)  
BIT_U0TINT    	DEFINE	(0x1<<4)  
BIT_U0RERR    	DEFINE	(0x1<<5)  
BIT_U1TINT    	DEFINE	(0x1<<6)
BIT_U1RERR    	DEFINE	(0x1<<7)  
BIT_GDMA0     	DEFINE	(0x1<<8)  
BIT_GDMA1     	DEFINE	(0x1<<9)  
BIT_TIMER0   	DEFINE	(0x1<<10)  
BIT_TIMER1   	DEFINE	(0x1<<11)  
BIT_HDLCTXA  	DEFINE	(0x1<<12)  
BIT_HDLCRXA  	DEFINE	(0x1<<13)  
BIT_HDLCTXB  	DEFINE	(0x1<<14)  
BIT_HDLCRXB  	DEFINE	(0x1<<15)  
BIT_ECBDMATx 	DEFINE	(0x1<<16)  
BIT_ECBDMARx 	DEFINE	(0x1<<17)  
BIT_ECMACTx  	DEFINE	(0x1<<18)  
BIT_ECMACRx  	DEFINE	(0x1<<19)  
BIT_i2cbus   	DEFINE	(0x1<<20)  
BIT_ALLMSK      DEFINE	(0xffffffff)