📄 4510addr.h
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//=============================================================================
// File Name : 4510addr.h
// Function : S3C4510 Define Address Register
// Program :
// Date : February 24, 2003
// Version : 0.0
// History
// 0.0 : Programming start (February 24,2003) -> SOP
//=============================================================================
#ifndef __4510ADDR_H__
#define __4510ADDR_H__
#ifndef __DEF_H__
#include "def.h"
#endif
#ifndef _OPTION_H
#include "option.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/*============================================================================================
;System Manager control
;============================================================================================*/
#define SYSCON (*(volatile unsigned *)0x03FF0000) //System configuration register ;0x07FFFF91
#define CLKCON (*(volatile unsigned *)0x03FF3000) //Clock control register ;0x00000000
#define EXTACON0 (*(volatile unsigned *)0x03FF3008) //External I/O timing register 1 ;0x00000000
#define EXTACON1 (*(volatile unsigned *)0x03FF300C) //External I/O timing register 2 ;0x00000000
#define EXTDBWTH (*(volatile unsigned *)0x03FF3010) //Data bus width of each bank ;0x00000000
#define ROMCON0 (*(volatile unsigned *)0x03FF3014) //ROM/SRAM/Flash bank 0 control register ;0x20000060
#define ROMCON1 (*(volatile unsigned *)0x03FF3018) //ROM/SRAM/Flash bank 1 control register ;0x00000060
#define ROMCON2 (*(volatile unsigned *)0x03FF301C) //ROM/SRAM/Flash bank 2 control register ;0x00000060
#define ROMCON3 (*(volatile unsigned *)0x03FF3020) //ROM/SRAM/Flash bank 3 control register ;0x00000060
#define ROMCON4 (*(volatile unsigned *)0x03FF3024) //ROM/SRAM/Flash bank 4 control register ;0x00000060
#define ROMCON5 (*(volatile unsigned *)0x03FF3028) //ROM/SRAM/Flash bank 5 control register ;0x00000060
#define DRAMCON0 (*(volatile unsigned *)0x03FF302C) //DRAM bank 0 control register ;0x00000000
#define DRAMCON1 (*(volatile unsigned *)0x03FF3030) //DRAM bank 0 control register ;0x00000000
#define DRAMCON2 (*(volatile unsigned *)0x03FF3034) //DRAM bank 0 control register ;0x00000000
#define DRAMCON3 (*(volatile unsigned *)0x03FF3038) //DRAM bank 0 control register ;0x00000000
#define REFEXTCON (*(volatile unsigned *)0x03FF303C) //Refresh and external I/O control register ;0x83FD0000
/*============================================================================================
;Ethernet(BDMA) registers
;============================================================================================*/
#define BDMATXCON (*(volatile unsigned *)0x03FF9000) // 0x00000000 ; Buffered DMA receive control register
#define BDMARXCON (*(volatile unsigned *)0x03FF9004) // 0x00000000 ; Buffered DMA transmit control register
#define BDMATXPTR (*(volatile unsigned *)0x03FF9008) // 0xFFFFFFFF ; Transmit trame descriptor start address
#define BDMARXPTR (*(volatile unsigned *)0x03FF900C) // 0xFFFFFFFF ; Receive frame descriptor start address
#define BDMARXLSZ (*(volatile unsigned *)0x03FF9010) // Undefined ; Receive frame maximum size
#define BDMASTAT (*(volatile unsigned *)0x03FF9014) // 0x00000000 ; Buffered DMA status
/*============================================================================================
;Ethernet(MAC) registers
;============================================================================================*/
#define MACON (*(volatile unsigned *)0x03FFA000) // 0x00000000 ; Ethernet MAC control register
#define CAMCON (*(volatile unsigned *)0x03FFA004) // 0x00000000 ; CAM control register
#define MACTXCON (*(volatile unsigned *)0x03FFA008) // 0x00000000 ; MAC transmit control register
#define MACTXSTAT (*(volatile unsigned *)0x03FFA00C) // 0x00000000 ; MAC transmit status register
#define MACRXCON (*(volatile unsigned *)0x03FFA010) // 0x00000000 ; MAC receive control register
#define MACRXSTAT (*(volatile unsigned *)0x03FFA014) // 0x00000000 ; MAC receive status register
#define STADATA (*(volatile unsigned *)0x03FFA018) // 0x00000000 ; Station management data
#define STACON (*(volatile unsigned *)0x03FFA01C) // 0x00006000 ; Station management control and address
#define CAMEN (*(volatile unsigned *)0x03FFA028) // 0x00000000 ; CAM enable register
#define EMISSCNT (*(volatile unsigned *)0x03FFA03C) // 0x00000000 ; Missed error count
#define EPZCNT (*(volatile unsigned *)0x03FFA040) // 0x00000000 ; Pause count
#define ERMPZCNT (*(volatile unsigned *)0x03FFA044) // 0x00000000 ; Read; Remote pause count
#define ETXSTAT (*(volatile unsigned *)0x03FF9040) // 0x00000000 ; Read; Transmit control frame status
/*============================================================================================
;HDLC Channel A Registers
;============================================================================================*/
#define HMODEA (*(volatile unsigned *)0x03FF7000) // 0x00000000 ; HDLC mode register
#define MCONA (*(volatile unsigned *)0x03FF7004) // 0x00000000 ; HDLC control register
#define HSTATA (*(volatile unsigned *)0x03FF7008) // 0x00000000 ; HDLC status register
#define HINTENA (*(volatile unsigned *)0x03FF700C) // 0x00000000 ; HDLC interrupt enable register
#define HTXFIFOCA (*(volatile unsigned *)0x03FF7010) // 0x00000000 ; TxFIFO frame continue register
#define HTXFIFOTA (*(volatile unsigned *)0x03FF7014) // 0x00000000 ; TxFIFO frame terminate register r
#define HRXFIFOA (*(volatile unsigned *)0x03FF7018) // 0x00000000 ; THDLC RxFIFO entry register
#define HBRGTCA (*(volatile unsigned *)0x03FF701C) // 0x00000000 ; HDLC Baud rate generate time constantr
#define HPRMBA (*(volatile unsigned *)0x03FF7020) // 0x00000000 ; HDLC Preamble Constant 0x00000000
#define HSADR0A (*(volatile unsigned *)0x03FF7024) // 0x00000000 ; HDLC station address 0
#define HSADR1A (*(volatile unsigned *)0x03FF7028) // 0x00000000 ; HDLC station address 1 0x00000000
#define HSADR2A (*(volatile unsigned *)0x03FF702C) // 0x00000000 ; HDLC station address 2
#define HSADR3A (*(volatile unsigned *)0x03FF7030) // 0x00000000 ; HDLC station address 3
#define HMASKA (*(volatile unsigned *)0x03FF7034) // 0x00000000 ; HDLC mask register
#define HDMATXPTRA (*(volatile unsigned *)0x03FF7038) // 0xFFFFFFFF ; DMA Tx buffer descriptor pointer
#define HDMARXPTRA (*(volatile unsigned *)0x03FF703C) // 0xFFFFFFFF ; DMA Rx buffer descriptor pointer
#define HMFLRA (*(volatile unsigned *)0x03FF7040) // 0xXXXX0000 ; Maximum frame length register
#define HRBSRA (*(volatile unsigned *)0x03FF7044) // 0xXXXX0000 ; DMA receive buffer size register
/*============================================================================================
;HDLC Channel B Registers
;============================================================================================*/
#define HMODEB (*(volatile unsigned *)0x03FF8000) // 0x00000000 ; HDLC mode register
#define MCONB (*(volatile unsigned *)0x03FF8004) // 0x00000000 ; HDLC control register
#define HSTATB (*(volatile unsigned *)0x03FF8008) // 0x000104000 ; HDLC status register
#define HINTENB (*(volatile unsigned *)0x03FF800C) // 0x00000000 ; HDLC interrupt enable register
#define HTXFIFOCB (*(volatile unsigned *)0x03FF8010) // 0x00000000 ; TxFIFO frame continue register
#define HRXFIFOB (*(volatile unsigned *)0x03FF8018) // 0x00000000 ; HDLC RxFIFO entry register
#define HBRGTCB (*(volatile unsigned *)0x03FF801C) // 0x00000000 ; HDLC Baud rate generate time constant
#define HPRMBB (*(volatile unsigned *)0x03FF8020) // 0x00000000 ; HDLC Preamble Constant
#define HSAR0B (*(volatile unsigned *)0x03FF8024) // 0x00000000 ; HDLC station address 0
#define HSAR1B (*(volatile unsigned *)0x03FF8028) // 0x00000000 ; HDLC station address 1
#define HSAR2B (*(volatile unsigned *)0x03FF802C) // 0x00000000 ; HDLC station address 2
#define HSAR3B (*(volatile unsigned *)0x03FF8030) // 0x00000000 ; HDLC station address 3
#define HMASKB (*(volatile unsigned *)0x03FF8034) // 0x00000000 ; HDLC mask register
#define HDMATXPTRB (*(volatile unsigned *)0x03FF8038) // 0xFFFFFFFF ; DMA Tx buffer descriptor pointer
#define HDMARXPTRB (*(volatile unsigned *)0x03FF803C) // 0xFFFFFFFF ; DMA Rx buffer descriptor pointer
#define HMFLRB (*(volatile unsigned *)0x03FF8040) // 0x00000000 ; Maximum frame length register
#define HRBSRB (*(volatile unsigned *)0x03FF8044) // 0x00000000 ; DMA receive buffer size register
/*============================================================================================
;I/O PORT CONTROL
;============================================================================================*/
#define IOPMOD (*(volatile unsigned *)0x03FF5000) //I/O port mode register ; 0x00000000 All Input
#define IOPCON (*(volatile unsigned *)0x03FF5004) //I/O port control registerr ; 0x00000000
#define IOPDATA (*(volatile unsigned *)0x03FF5008) //I/O port data register ; Undefined
/*============================================================================================
;S3C4510B interrupt sources
;============================================================================================*/
#define INTMOD (*(volatile unsigned *)0x03FF4000) //Interrupt mode register ; 0x00000000
#define INTPND (*(volatile unsigned *)0x03FF4004) //Interrupt pending register ; 0x00000000
#define INTMSK (*(volatile unsigned *)0x03FF4008) //Interrupt mask register ; 0x003FFFFF
#define INTPRI0 (*(volatile unsigned *)0x03FF400C) //Interrupt priority register 0 ; 0x03020100
#define INTPRI1 (*(volatile unsigned *)0x03FF4010) //Interrupt priority register 1 ; 0x07060504
#define INTPRI2 (*(volatile unsigned *)0x03FF4014) //Interrupt priority register 2 ; 0x0B0A0908
#define INTPRI3 (*(volatile unsigned *)0x03FF4018) //Interrupt priority register 3 ; 0x0F0E0D0C
#define INTPRI4 (*(volatile unsigned *)0x03FF401C) //nterrupt priority register 4 ; 0x13121110
#define INTPRI5 (*(volatile unsigned *)0x03FF4020) //Interrupt priority register 5 ; 0x00000014
#define INTOFFSET (*(volatile unsigned *)0x03FF4024) //Interrupt offset register ; 0x00000054
#define INTOSET_FIQ (*(volatile unsigned *)0x03FF4030) //FIQ Interrupt offset register ; 0x00000054
#define INTOSET_IRQ (*(volatile unsigned *)0x03FF4034) //IRQ Interrupt offset register ; 0x00000054
/*============================================================================================
;I2C Bus control registers
;============================================================================================*/
#define IICCON (*(volatile unsigned *)0x03FFF000) // 0x00000000 ; I2C bus control status register 0x00000054
#define IICBUF (*(volatile unsigned *)0x03FFF004) // Undefined ; I2C bus shift buffer register
#define IICPS (*(volatile unsigned *)0x03FFF008) // 0x00000000 ; I2C bus prescaler register
#define IICCOUNT (*(volatile unsigned *)0x03FFF00C) // 0x00000000 ; I2C bus prescaler counter register
/*============================================================================================
;GDMA control registers
;============================================================================================*/
#define GDMACON0 (*(volatile unsigned *)0x03FFB000) // 0x00000000; GDMA controller channel 0 control register
#define GDMACON1 (*(volatile unsigned *)0x03FFC000) // 0x00000000; GDMA controller channel 1 control register
#define GDMASRC0 (*(volatile unsigned *)0x03FFB004) // Undefined; GDMA channel 0 source address register
#define GDMADST0 (*(volatile unsigned *)0x03FFB008) // Undefined; GDMA channel 0 destination address register
#define GDMASRC1 (*(volatile unsigned *)0x03FFC004) // Undefined; GDMA channel 1 source address register
#define GDMADST1 (*(volatile unsigned *)0x03FFC008) // Undefined; GDMA channel 1 destination address register
#define GDMACNT0 (*(volatile unsigned *)0x03FFB00C) // Undefined; GDMA channel 0 transfer count register
#define GDMACNT1 (*(volatile unsigned *)0x03FFC00C) // Undefined; GDMA channel 1 transfer count register
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