qam.tan.qmsg

实现qam调制解调实现qam调制解调实现qam调制解调

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CNT_CLK " "Info: Assuming node \"CNT_CLK\" is an undefined clock" {  } { { "QAM.bdf" "" { Schematic "D:/杨淼的毕业设计/bs/QAM.bdf" { { 16 -112 56 32 "CNT_CLK" "" } } } } { "d:/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/quartus60/win/Assignment Editor.qase" 1 { { 0 "CNT_CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "DIV_CLK_2:inst15\|clk_out " "Info: Detected ripple clock \"DIV_CLK_2:inst15\|clk_out\" as buffer" {  } { { "DIV_CLK_2.tdf" "" { Text "D:/杨淼的毕业设计/bs/DIV_CLK_2.tdf" 7 3 0 } } { "d:/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/quartus60/win/Assignment Editor.qase" 1 { { 0 "DIV_CLK_2:inst15\|clk_out" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "74393:inst10\|9 " "Info: Detected ripple clock \"74393:inst10\|9\" as buffer" {  } { { "74393.bdf" "" { Schematic "d:/quartus60/libraries/others/maxplus2/74393.bdf" { { 400 440 504 480 "9" "" } } } } { "d:/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/quartus60/win/Assignment Editor.qase" 1 { { 0 "74393:inst10\|9" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "74393:inst10\|28 " "Info: Detected ripple clock \"74393:inst10\|28\" as buffer" {  } { { "74393.bdf" "" { Schematic "d:/quartus60/libraries/others/maxplus2/74393.bdf" { { 528 440 504 608 "28" "" } } } } { "d:/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/quartus60/win/Assignment Editor.qase" 1 { { 0 "74393:inst10\|28" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CNT_CLK register register M_GENERAToR:inst\|bit\[2\] M_GENERAToR:inst\|bit\[3\] 420.17 MHz Internal " "Info: Clock \"CNT_CLK\" Internal fmax is restricted to 420.17 MHz between source register \"M_GENERAToR:inst\|bit\[2\]\" and destination register \"M_GENERAToR:inst\|bit\[3\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.961 ns + Longest register register " "Info: + Longest register to register delay is 0.961 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns M_GENERAToR:inst\|bit\[2\] 1 REG LCFF_X12_Y12_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y12_N9; Fanout = 1; REG Node = 'M_GENERAToR:inst\|bit\[2\]'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "" { M_GENERAToR:inst|bit[2] } "NODE_NAME" } } { "M_GENERAToR.tdf" "" { Text "D:/杨淼的毕业设计/bs/M_GENERAToR.tdf" 7 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.728 ns) + CELL(0.149 ns) 0.877 ns M_GENERAToR:inst\|bit\[3\]~feeder 2 COMB LCCOMB_X10_Y12_N12 1 " "Info: 2: + IC(0.728 ns) + CELL(0.149 ns) = 0.877 ns; Loc. = LCCOMB_X10_Y12_N12; Fanout = 1; COMB Node = 'M_GENERAToR:inst\|bit\[3\]~feeder'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "0.877 ns" { M_GENERAToR:inst|bit[2] M_GENERAToR:inst|bit[3]~feeder } "NODE_NAME" } } { "M_GENERAToR.tdf" "" { Text "D:/杨淼的毕业设计/bs/M_GENERAToR.tdf" 7 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.961 ns M_GENERAToR:inst\|bit\[3\] 3 REG LCFF_X10_Y12_N13 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.961 ns; Loc. = LCFF_X10_Y12_N13; Fanout = 1; REG Node = 'M_GENERAToR:inst\|bit\[3\]'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { M_GENERAToR:inst|bit[3]~feeder M_GENERAToR:inst|bit[3] } "NODE_NAME" } } { "M_GENERAToR.tdf" "" { Text "D:/杨淼的毕业设计/bs/M_GENERAToR.tdf" 7 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.233 ns ( 24.25 % ) " "Info: Total cell delay = 0.233 ns ( 24.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.728 ns ( 75.75 % ) " "Info: Total interconnect delay = 0.728 ns ( 75.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "0.961 ns" { M_GENERAToR:inst|bit[2] M_GENERAToR:inst|bit[3]~feeder M_GENERAToR:inst|bit[3] } "NODE_NAME" } } { "d:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus60/win/Technology_Viewer.qrui" "0.961 ns" { M_GENERAToR:inst|bit[2] M_GENERAToR:inst|bit[3]~feeder M_GENERAToR:inst|bit[3] } { 0.000ns 0.728ns 0.000ns } { 0.000ns 0.149ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.003 ns - Smallest " "Info: - Smallest clock skew is -0.003 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CNT_CLK destination 5.535 ns + Shortest register " "Info: + Shortest clock path from clock \"CNT_CLK\" to destination register is 5.535 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns CNT_CLK 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CNT_CLK'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "" { CNT_CLK } "NODE_NAME" } } { "QAM.bdf" "" { Schematic "D:/杨淼的毕业设计/bs/QAM.bdf" { { 16 -112 56 32 "CNT_CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns CNT_CLK~clkctrl 2 COMB CLKCTRL_G2 5 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'CNT_CLK~clkctrl'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { CNT_CLK CNT_CLK~clkctrl } "NODE_NAME" } } { "QAM.bdf" "" { Schematic "D:/杨淼的毕业设计/bs/QAM.bdf" { { 16 -112 56 32 "CNT_CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.702 ns) + CELL(0.787 ns) 2.600 ns 74393:inst10\|9 3 REG LCFF_X27_Y7_N3 2 " "Info: 3: + IC(0.702 ns) + CELL(0.787 ns) = 2.600 ns; Loc. = LCFF_X27_Y7_N3; Fanout = 2; REG Node = '74393:inst10\|9'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "1.489 ns" { CNT_CLK~clkctrl 74393:inst10|9 } "NODE_NAME" } } { "74393.bdf" "" { Schematic "d:/quartus60/libraries/others/maxplus2/74393.bdf" { { 400 440 504 480 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.293 ns) + CELL(0.787 ns) 3.680 ns 74393:inst10\|28 4 REG LCFF_X27_Y7_N7 3 " "Info: 4: + IC(0.293 ns) + CELL(0.787 ns) = 3.680 ns; Loc. = LCFF_X27_Y7_N7; Fanout = 3; REG Node = '74393:inst10\|28'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "1.080 ns" { 74393:inst10|9 74393:inst10|28 } "NODE_NAME" } } { "74393.bdf" "" { Schematic "d:/quartus60/libraries/others/maxplus2/74393.bdf" { { 528 440 504 608 "28" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.589 ns) + CELL(0.000 ns) 4.269 ns 74393:inst10\|28~clkctrl 5 COMB CLKCTRL_G5 23 " "Info: 5: + IC(0.589 ns) + CELL(0.000 ns) = 4.269 ns; Loc. = CLKCTRL_G5; Fanout = 23; COMB Node = '74393:inst10\|28~clkctrl'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "0.589 ns" { 74393:inst10|28 74393:inst10|28~clkctrl } "NODE_NAME" } } { "74393.bdf" "" { Schematic "d:/quartus60/libraries/others/maxplus2/74393.bdf" { { 528 440 504 608 "28" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.537 ns) 5.535 ns M_GENERAToR:inst\|bit\[3\] 6 REG LCFF_X10_Y12_N13 1 " "Info: 6: + IC(0.729 ns) + CELL(0.537 ns) = 5.535 ns; Loc. = LCFF_X10_Y12_N13; Fanout = 1; REG Node = 'M_GENERAToR:inst\|bit\[3\]'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "1.266 ns" { 74393:inst10|28~clkctrl M_GENERAToR:inst|bit[3] } "NODE_NAME" } } { "M_GENERAToR.tdf" "" { Text "D:/杨淼的毕业设计/bs/M_GENERAToR.tdf" 7 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.100 ns ( 56.01 % ) " "Info: Total cell delay = 3.100 ns ( 56.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.435 ns ( 43.99 % ) " "Info: Total interconnect delay = 2.435 ns ( 43.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "5.535 ns" { CNT_CLK CNT_CLK~clkctrl 74393:inst10|9 74393:inst10|28 74393:inst10|28~clkctrl M_GENERAToR:inst|bit[3] } "NODE_NAME" } } { "d:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus60/win/Technology_Viewer.qrui" "5.535 ns" { CNT_CLK CNT_CLK~combout CNT_CLK~clkctrl 74393:inst10|9 74393:inst10|28 74393:inst10|28~clkctrl M_GENERAToR:inst|bit[3] } { 0.000ns 0.000ns 0.122ns 0.702ns 0.293ns 0.589ns 0.729ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CNT_CLK source 5.538 ns - Longest register " "Info: - Longest clock path from clock \"CNT_CLK\" to source register is 5.538 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns CNT_CLK 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CNT_CLK'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "" { CNT_CLK } "NODE_NAME" } } { "QAM.bdf" "" { Schematic "D:/杨淼的毕业设计/bs/QAM.bdf" { { 16 -112 56 32 "CNT_CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns CNT_CLK~clkctrl 2 COMB CLKCTRL_G2 5 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'CNT_CLK~clkctrl'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { CNT_CLK CNT_CLK~clkctrl } "NODE_NAME" } } { "QAM.bdf" "" { Schematic "D:/杨淼的毕业设计/bs/QAM.bdf" { { 16 -112 56 32 "CNT_CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.702 ns) + CELL(0.787 ns) 2.600 ns 74393:inst10\|9 3 REG LCFF_X27_Y7_N3 2 " "Info: 3: + IC(0.702 ns) + CELL(0.787 ns) = 2.600 ns; Loc. = LCFF_X27_Y7_N3; Fanout = 2; REG Node = '74393:inst10\|9'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "1.489 ns" { CNT_CLK~clkctrl 74393:inst10|9 } "NODE_NAME" } } { "74393.bdf" "" { Schematic "d:/quartus60/libraries/others/maxplus2/74393.bdf" { { 400 440 504 480 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.293 ns) + CELL(0.787 ns) 3.680 ns 74393:inst10\|28 4 REG LCFF_X27_Y7_N7 3 " "Info: 4: + IC(0.293 ns) + CELL(0.787 ns) = 3.680 ns; Loc. = LCFF_X27_Y7_N7; Fanout = 3; REG Node = '74393:inst10\|28'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "1.080 ns" { 74393:inst10|9 74393:inst10|28 } "NODE_NAME" } } { "74393.bdf" "" { Schematic "d:/quartus60/libraries/others/maxplus2/74393.bdf" { { 528 440 504 608 "28" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.589 ns) + CELL(0.000 ns) 4.269 ns 74393:inst10\|28~clkctrl 5 COMB CLKCTRL_G5 23 " "Info: 5: + IC(0.589 ns) + CELL(0.000 ns) = 4.269 ns; Loc. = CLKCTRL_G5; Fanout = 23; COMB Node = '74393:inst10\|28~clkctrl'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "0.589 ns" { 74393:inst10|28 74393:inst10|28~clkctrl } "NODE_NAME" } } { "74393.bdf" "" { Schematic "d:/quartus60/libraries/others/maxplus2/74393.bdf" { { 528 440 504 608 "28" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.537 ns) 5.538 ns M_GENERAToR:inst\|bit\[2\] 6 REG LCFF_X12_Y12_N9 1 " "Info: 6: + IC(0.732 ns) + CELL(0.537 ns) = 5.538 ns; Loc. = LCFF_X12_Y12_N9; Fanout = 1; REG Node = 'M_GENERAToR:inst\|bit\[2\]'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "1.269 ns" { 74393:inst10|28~clkctrl M_GENERAToR:inst|bit[2] } "NODE_NAME" } } { "M_GENERAToR.tdf" "" { Text "D:/杨淼的毕业设计/bs/M_GENERAToR.tdf" 7 6 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.100 ns ( 55.98 % ) " "Info: Total cell delay = 3.100 ns ( 55.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.438 ns ( 44.02 % ) " "Info: Total interconnect delay = 2.438 ns ( 44.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "5.538 ns" { CNT_CLK CNT_CLK~clkctrl 74393:inst10|9 74393:inst10|28 74393:inst10|28~clkctrl M_GENERAToR:inst|bit[2] } "NODE_NAME" } } { "d:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus60/win/Technology_Viewer.qrui" "5.538 ns" { CNT_CLK CNT_CLK~combout CNT_CLK~clkctrl 74393:inst10|9 74393:inst10|28 74393:inst10|28~clkctrl M_GENERAToR:inst|bit[2] } { 0.000ns 0.000ns 0.122ns 0.702ns 0.293ns 0.589ns 0.732ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "5.535 ns" { CNT_CLK CNT_CLK~clkctrl 74393:inst10|9 74393:inst10|28 74393:inst10|28~clkctrl M_GENERAToR:inst|bit[3] } "NODE_NAME" } } { "d:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus60/win/Technology_Viewer.qrui" "5.535 ns" { CNT_CLK CNT_CLK~combout CNT_CLK~clkctrl 74393:inst10|9 74393:inst10|28 74393:inst10|28~clkctrl M_GENERAToR:inst|bit[3] } { 0.000ns 0.000ns 0.122ns 0.702ns 0.293ns 0.589ns 0.729ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.787ns 0.000ns 0.537ns } } } { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "5.538 ns" { CNT_CLK CNT_CLK~clkctrl 74393:inst10|9 74393:inst10|28 74393:inst10|28~clkctrl M_GENERAToR:inst|bit[2] } "NODE_NAME" } } { "d:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus60/win/Technology_Viewer.qrui" "5.538 ns" { CNT_CLK CNT_CLK~combout CNT_CLK~clkctrl 74393:inst10|9 74393:inst10|28 74393:inst10|28~clkctrl M_GENERAToR:inst|bit[2] } { 0.000ns 0.000ns 0.122ns 0.702ns 0.293ns 0.589ns 0.732ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "M_GENERAToR.tdf" "" { Text "D:/杨淼的毕业设计/bs/M_GENERAToR.tdf" 7 6 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "M_GENERAToR.tdf" "" { Text "D:/杨淼的毕业设计/bs/M_GENERAToR.tdf" 7 6 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "0.961 ns" { M_GENERAToR:inst|bit[2] M_GENERAToR:inst|bit[3]~feeder M_GENERAToR:inst|bit[3] } "NODE_NAME" } } { "d:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus60/win/Technology_Viewer.qrui" "0.961 ns" { M_GENERAToR:inst|bit[2] M_GENERAToR:inst|bit[3]~feeder M_GENERAToR:inst|bit[3] } { 0.000ns 0.728ns 0.000ns } { 0.000ns 0.149ns 0.084ns } } } { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "5.535 ns" { CNT_CLK CNT_CLK~clkctrl 74393:inst10|9 74393:inst10|28 74393:inst10|28~clkctrl M_GENERAToR:inst|bit[3] } "NODE_NAME" } } { "d:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus60/win/Technology_Viewer.qrui" "5.535 ns" { CNT_CLK CNT_CLK~combout CNT_CLK~clkctrl 74393:inst10|9 74393:inst10|28 74393:inst10|28~clkctrl M_GENERAToR:inst|bit[3] } { 0.000ns 0.000ns 0.122ns 0.702ns 0.293ns 0.589ns 0.729ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.787ns 0.000ns 0.537ns } } } { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "5.538 ns" { CNT_CLK CNT_CLK~clkctrl 74393:inst10|9 74393:inst10|28 74393:inst10|28~clkctrl M_GENERAToR:inst|bit[2] } "NODE_NAME" } } { "d:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus60/win/Technology_Viewer.qrui" "5.538 ns" { CNT_CLK CNT_CLK~combout CNT_CLK~clkctrl 74393:inst10|9 74393:inst10|28 74393:inst10|28~clkctrl M_GENERAToR:inst|bit[2] } { 0.000ns 0.000ns 0.122ns 0.702ns 0.293ns 0.589ns 0.732ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "" { M_GENERAToR:inst|bit[3] } "NODE_NAME" } } { "d:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus60/win/Technology_Viewer.qrui" "" { M_GENERAToR:inst|bit[3] } {  } {  } } } { "M_GENERAToR.tdf" "" { Text "D:/杨淼的毕业设计/bs/M_GENERAToR.tdf" 7 6 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}