qam.map.qmsg

实现qam调制解调实现qam调制解调实现qam调制解调

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../quartus60/libraries/others/maxplus2/74393.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../quartus60/libraries/others/maxplus2/74393.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74393 " "Info: Found entity 1: 74393" {  } { { "74393.bdf" "" { Schematic "d:/quartus60/libraries/others/maxplus2/74393.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74393 74393:inst10 " "Info: Elaborating entity \"74393\" for hierarchy \"74393:inst10\"" {  } { { "QAM.bdf" "inst10" { Schematic "D:/杨淼的毕业设计/bs/QAM.bdf" { { -32 224 344 144 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "74393:inst10 " "Info: Elaborated megafunction instantiation \"74393:inst10\"" {  } { { "QAM.bdf" "" { Schematic "D:/杨淼的毕业设计/bs/QAM.bdf" { { -32 224 344 144 "inst10" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "compose.bdf 1 1 " "Warning: Using design file compose.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 compose " "Info: Found entity 1: compose" {  } { { "compose.bdf" "" { Schematic "D:/杨淼的毕业设计/bs/compose.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "compose compose:inst5 " "Info: Elaborating entity \"compose\" for hierarchy \"compose:inst5\"" {  } { { "QAM.bdf" "inst5" { Schematic "D:/杨淼的毕业设计/bs/QAM.bdf" { { 208 832 976 336 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add compose:inst5\|add:inst43 " "Info: Elaborating entity \"add\" for hierarchy \"compose:inst5\|add:inst43\"" {  } { { "compose.bdf" "inst43" { Schematic "D:/杨淼的毕业设计/bs/compose.bdf" { { 184 1272 1400 376 "inst43" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "zhuanhuan2 compose:inst5\|zhuanhuan2:inst35 " "Info: Elaborating entity \"zhuanhuan2\" for hierarchy \"compose:inst5\|zhuanhuan2:inst35\"" {  } { { "compose.bdf" "inst35" { Schematic "D:/杨淼的毕业设计/bs/compose.bdf" { { -552 1080 1176 -360 "inst35" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cos compose:inst5\|cos:inst27 " "Info: Elaborating entity \"cos\" for hierarchy \"compose:inst5\|cos:inst27\"" {  } { { "compose.bdf" "inst27" { Schematic "D:/杨淼的毕业设计/bs/compose.bdf" { { -552 960 1056 -360 "inst27" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "zhuanhuan1 compose:inst5\|zhuanhuan1:inst15 " "Info: Elaborating entity \"zhuanhuan1\" for hierarchy \"compose:inst5\|zhuanhuan1:inst15\"" {  } { { "compose.bdf" "inst15" { Schematic "D:/杨淼的毕业设计/bs/compose.bdf" { { -536 832 928 -408 "inst15" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "4xuan1 compose:inst5\|4xuan1:inst " "Info: Elaborating entity \"4xuan1\" for hierarchy \"compose:inst5\|4xuan1:inst\"" {  } { { "compose.bdf" "inst" { Schematic "D:/杨淼的毕业设计/bs/compose.bdf" { { 24 600 728 152 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cnt_4 compose:inst5\|cnt_4:inst2 " "Info: Elaborating entity \"cnt_4\" for hierarchy \"compose:inst5\|cnt_4:inst2\"" {  } { { "compose.bdf" "inst2" { Schematic "D:/杨淼的毕业设计/bs/compose.bdf" { { 24 456 576 152 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "zhuanhuan compose:inst5\|zhuanhuan:inst5 " "Info: Elaborating entity \"zhuanhuan\" for hierarchy \"compose:inst5\|zhuanhuan:inst5\"" {  } { { "compose.bdf" "inst5" { Schematic "D:/杨淼的毕业设计/bs/compose.bdf" { { 40 280 376 168 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "table1 compose:inst5\|table1:inst9 " "Info: Elaborating entity \"table1\" for hierarchy \"compose:inst5\|table1:inst9\"" {  } { { "compose.bdf" "inst9" { Schematic "D:/杨淼的毕业设计/bs/compose.bdf" { { 40 136 232 232 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cos1 compose:inst5\|cos1:inst4 " "Info: Elaborating entity \"cos1\" for hierarchy \"compose:inst5\|cos1:inst4\"" {  } { { "compose.bdf" "inst4" { Schematic "D:/杨淼的毕业设计/bs/compose.bdf" { { -352 960 1056 -160 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cos2 compose:inst5\|cos2:inst29 " "Info: Elaborating entity \"cos2\" for hierarchy \"compose:inst5\|cos2:inst29\"" {  } { { "compose.bdf" "inst29" { Schematic "D:/杨淼的毕业设计/bs/compose.bdf" { { -152 960 1056 40 "inst29" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cos3 compose:inst5\|cos3:inst30 " "Info: Elaborating entity \"cos3\" for hierarchy \"compose:inst5\|cos3:inst30\"" {  } { { "compose.bdf" "inst30" { Schematic "D:/杨淼的毕业设计/bs/compose.bdf" { { 56 960 1056 248 "inst30" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sin compose:inst5\|sin:inst31 " "Info: Elaborating entity \"sin\" for hierarchy \"compose:inst5\|sin:inst31\"" {  } { { "compose.bdf" "inst31" { Schematic "D:/杨淼的毕业设计/bs/compose.bdf" { { 288 960 1056 480 "inst31" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sin1 compose:inst5\|sin1:inst32 " "Info: Elaborating entity \"sin1\" for hierarchy \"compose:inst5\|sin1:inst32\"" {  } { { "compose.bdf" "inst32" { Schematic "D:/杨淼的毕业设计/bs/compose.bdf" { { 488 960 1056 680 "inst32" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sin2 compose:inst5\|sin2:inst33 " "Info: Elaborating entity \"sin2\" for hierarchy \"compose:inst5\|sin2:inst33\"" {  } { { "compose.bdf" "inst33" { Schematic "D:/杨淼的毕业设计/bs/compose.bdf" { { 696 960 1056 888 "inst33" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sin3 compose:inst5\|sin3:inst34 " "Info: Elaborating entity \"sin3\" for hierarchy \"compose:inst5\|sin3:inst34\"" {  } { { "compose.bdf" "inst34" { Schematic "D:/杨淼的毕业设计/bs/compose.bdf" { { 896 960 1056 1088 "inst34" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DIV_CLK_2 DIV_CLK_2:inst15 " "Info: Elaborating entity \"DIV_CLK_2\" for hierarchy \"DIV_CLK_2:inst15\"" {  } { { "QAM.bdf" "inst15" { Schematic "D:/杨淼的毕业设计/bs/QAM.bdf" { { -120 536 656 -24 "inst15" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "d.bdf 1 1 " "Warning: Using design file d.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 d " "Info: Found entity 1: d" {  } { { "d.bdf" "" { Schematic "D:/杨淼的毕业设计/bs/d.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "d d:inst3 " "Info: Elaborating entity \"d\" for hierarchy \"d:inst3\"" {  } { { "QAM.bdf" "inst3" { Schematic "D:/杨淼的毕业设计/bs/QAM.bdf" { { 224 672 768 352 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "fenli.bdf 1 1 " "Warning: Using design file fenli.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 fenli " "Info: Found entity 1: fenli" {  } { { "fenli.bdf" "" { Schematic "D:/杨淼的毕业设计/bs/fenli.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fenli fenli:inst2 " "Info: Elaborating entity \"fenli\" for hierarchy \"fenli:inst2\"" {  } { { "QAM.bdf" "inst2" { Schematic "D:/杨淼的毕业设计/bs/QAM.bdf" { { 120 464 560 216 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lock.bdf 1 1 " "Warning: Using design file lock.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lock " "Info: Found entity 1: lock" {  } { { "lock.bdf" "" { Schematic "D:/杨淼的毕业设计/bs/lock.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lock lock:inst11 " "Info: Elaborating entity \"lock\" for hierarchy \"lock:inst11\"" {  } { { "QAM.bdf" "inst11" { Schematic "D:/杨淼的毕业设计/bs/QAM.bdf" { { 248 256 352 344 "inst11" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "compose:inst5\|cnt_4:inst2\|count\[3\] compose:inst5\|cnt_4:inst1\|count\[3\] " "Info: Duplicate register \"compose:inst5\|cnt_4:inst2\|count\[3\]\" merged to single register \"compose:inst5\|cnt_4:inst1\|count\[3\]\"" {  } { { "cnt_4.tdf" "" { Text "D:/杨淼的毕业设计/bs/cnt_4.tdf" 10 10 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "compose:inst5\|cnt_4:inst2\|count\[2\] compose:inst5\|cnt_4:inst1\|count\[2\] " "Info: Duplicate register \"compose:inst5\|cnt_4:inst2\|count\[2\]\" merged to single register \"compose:inst5\|cnt_4:inst1\|count\[2\]\"" {  } { { "cnt_4.tdf" "" { Text "D:/杨淼的毕业设计/bs/cnt_4.tdf" 10 10 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "compose:inst5\|cnt_4:inst2\|count\[1\] compose:inst5\|cnt_4:inst1\|count\[1\] " "Info: Duplicate register \"compose:inst5\|cnt_4:inst2\|count\[1\]\" merged to single register \"compose:inst5\|cnt_4:inst1\|count\[1\]\"" {  } { { "cnt_4.tdf" "" { Text "D:/杨淼的毕业设计/bs/cnt_4.tdf" 10 10 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "compose:inst5\|cnt_4:inst2\|count\[0\] compose:inst5\|cnt_4:inst1\|count\[0\] " "Info: Duplicate register \"compose:inst5\|cnt_4:inst2\|count\[0\]\" merged to single register \"compose:inst5\|cnt_4:inst1\|count\[0\]\"" {  } { { "cnt_4.tdf" "" { Text "D:/杨淼的毕业设计/bs/cnt_4.tdf" 10 10 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "139 " "Info: Implemented 139 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "128 " "Info: Implemented 128 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 15 09:18:15 2008 " "Info: Processing ended: Sun Jun 15 09:18:15 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}