📄 led.vhd
字号:
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:47:05 03/15/07
-- Design Name:
-- Module Name: led - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity led is
port (
main_clk: in STD_LOGIC;
lclk: out STD_LOGIC;
led1: out STD_LOGIC;
led2: out STD_LOGIC
);
end led;
architecture Behavioral of led is
begin
lclk<= main_clk;
led2<='0';
led1<='1';
end Behavioral;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -