ss.timesim_vhw

采用9054做为板卡与计算机通信的媒介

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 7.1.04i
--  \   \         Application : ISE Foundation
--  /   /         Filename : ss.timesim_vhw
-- /___/   /\     Timestamp : Thu Mar 15 20:28:52 2007
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: ss
--Device: Xilinx
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY ss IS
END ss;

ARCHITECTURE testbench_arch OF ss IS
    COMPONENT a90541
        PORT (
            main_clk : In std_logic;
            lholda : Out std_logic;
            lhold : In std_logic;
            lclk : Out std_logic;
            ready : Out std_logic;
            blast : In std_logic;
            wr : In std_logic;
            ads : In std_logic;
            cpld : In std_logic;
            led1 : Out std_logic;
            led2 : Out std_logic;
            led : Out std_logic_vector (7 DownTo 0);
            lint : Out std_logic;
            ld : InOut std_logic_vector (7 DownTo 0);
            la : In std_logic_vector (14 DownTo 0);
            ce : Out std_logic;
            we : Out std_logic;
            oe : Out std_logic;
            onoffa : In std_logic;
            sa : Out std_logic_vector (14 DownTo 0)
        );
    END COMPONENT;

    SIGNAL main_clk : std_logic := '0';
    SIGNAL lholda : std_logic := '0';
    SIGNAL lhold : std_logic := '0';
    SIGNAL lclk : std_logic := '0';
    SIGNAL ready : std_logic := '0';
    SIGNAL blast : std_logic := '1';
    SIGNAL wr : std_logic := '0';
    SIGNAL ads : std_logic := '1';
    SIGNAL cpld : std_logic := '0';
    SIGNAL led1 : std_logic := '0';
    SIGNAL led2 : std_logic := '0';
    SIGNAL led : std_logic_vector (7 DownTo 0) := "00000000";
    SIGNAL lint : std_logic := '0';
    SIGNAL ld : std_logic_vector (7 DownTo 0) := "00000000";
    SIGNAL la : std_logic_vector (14 DownTo 0) := "000000000000000";
    SIGNAL ce : std_logic := '0';
    SIGNAL we : std_logic := '0';
    SIGNAL oe : std_logic := '0';
    SIGNAL onoffa : std_logic := '0';
    SIGNAL sa : std_logic_vector (14 DownTo 0) := "000000000000000";

    SHARED VARIABLE TX_ERROR : INTEGER := 0;
    SHARED VARIABLE TX_OUT : LINE;

    constant PERIOD : time := 50 ns;
    constant DUTY_CYCLE : real := 0.5;
    constant OFFSET : time := 0 ns;

    BEGIN
        UUT : a90541
        PORT MAP (
            main_clk => main_clk,
            lholda => lholda,
            lhold => lhold,
            lclk => lclk,
            ready => ready,
            blast => blast,
            wr => wr,
            ads => ads,
            cpld => cpld,
            led1 => led1,
            led2 => led2,
            led => led,
            lint => lint,
            ld => ld,
            la => la,
            ce => ce,
            we => we,
            oe => oe,
            onoffa => onoffa,
            sa => sa
        );

        PROCESS    -- clock process for main_clk
        BEGIN
            WAIT for OFFSET;
            CLOCK_LOOP : LOOP
                main_clk <= '0';
                WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
                main_clk <= '1';
                WAIT FOR (PERIOD * DUTY_CYCLE);
            END LOOP CLOCK_LOOP;
        END PROCESS;

        PROCESS
            PROCEDURE CHECK_ce(
                next_ce : std_logic;
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
                BEGIN
                IF (ce /= next_ce) THEN
                    STD.TEXTIO.write(TX_LOC, string'("Error at time="));
                    STD.TEXTIO.write(TX_LOC, TX_TIME);
                    STD.TEXTIO.write(TX_LOC, string'("ns ce="));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, ce);
                    STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_ce);
                    STD.TEXTIO.write(TX_LOC, string'(" "));
                    TX_STR(TX_LOC.all'range) := TX_LOC.all;
                    STD.TEXTIO.Deallocate(TX_LOC);
                    ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
                    TX_ERROR := TX_ERROR + 1;
                END IF;
            END;
            PROCEDURE CHECK_lclk(
                next_lclk : std_logic;
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
                BEGIN
                IF (lclk /= next_lclk) THEN
                    STD.TEXTIO.write(TX_LOC, string'("Error at time="));
                    STD.TEXTIO.write(TX_LOC, TX_TIME);
                    STD.TEXTIO.write(TX_LOC, string'("ns lclk="));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, lclk);
                    STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_lclk);
                    STD.TEXTIO.write(TX_LOC, string'(" "));
                    TX_STR(TX_LOC.all'range) := TX_LOC.all;
                    STD.TEXTIO.Deallocate(TX_LOC);
                    ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
                    TX_ERROR := TX_ERROR + 1;
                END IF;
            END;
            PROCEDURE CHECK_led(
                next_led : std_logic_vector (7 DownTo 0);
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
                BEGIN
                IF (led /= next_led) THEN
                    STD.TEXTIO.write(TX_LOC, string'("Error at time="));
                    STD.TEXTIO.write(TX_LOC, TX_TIME);
                    STD.TEXTIO.write(TX_LOC, string'("ns led="));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, led);
                    STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_led);
                    STD.TEXTIO.write(TX_LOC, string'(" "));
                    TX_STR(TX_LOC.all'range) := TX_LOC.all;
                    STD.TEXTIO.Deallocate(TX_LOC);
                    ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
                    TX_ERROR := TX_ERROR + 1;
                END IF;
            END;
            PROCEDURE CHECK_led1(
                next_led1 : std_logic;
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
                BEGIN
                IF (led1 /= next_led1) THEN
                    STD.TEXTIO.write(TX_LOC, string'("Error at time="));
                    STD.TEXTIO.write(TX_LOC, TX_TIME);
                    STD.TEXTIO.write(TX_LOC, string'("ns led1="));
                    IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, led1);
                    STD.TEXTIO.write(TX_LOC, string'(", Expected = "));