__projnav.log

来自「采用9054做为板卡与计算机通信的媒介」· LOG 代码 · 共 1,812 行 · 第 1/5 页

LOG
1,812 行
字号
12345
Release 7.1.04i - ngdbuild H.42Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.Command Line: ngdbuild -dd _ngo -i -p xc9500xl a90541.ngc a90541.ngd Reading NGO file 'D:/study/PCI/a90541.ngc' ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary:  Number of errors:     0  Number of warnings:   0Writing NGD file "a90541.ngd" ...Writing NGDBUILD log file "a90541.bld"...NGDBUILD done.
Started process "Fit".Release 7.1.04i - CPLD Optimizer/Partitioner H.42Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.Considering device XC95288XL-10-TQ144.Flattening design..Timing optimizationTiming driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 44 equations into 16 function blocks.......................................................................................................................................................................................................................................................................................................................................................................................................................Design a90541 has been optimized and fit into device XC95288XL-10-TQ144.
Started process "Generate Post-Fit Simulation Model".Release 7.1.04i - CPLD Timing Simulation Interface H.42Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.Creating NGA for simulation.Speed File: Version 3.0
Release 7.1.04i - netgen H.42Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.Command Line: netgen -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sima90541.nga a90541_timesim.vhd  Reading design 'a90541.nga' ...Flattening design ...Processing design ...   Preping design's networks ...  Preping design's macros ...Writing VHDL netlist 'a90541_timesim.vhd' ...Writing VHDL SDF file 'a90541_timesim.sdf' ...INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx SIMPRIM   simulation primitives and has to be used with SIMPRIM library for correct   compilation and simulation. Number of warnings: 0Number of info messages: 1Total memory usage is 44204 kilobytesCreated netgen log file 'a90541_timesim.nlf'.



Project Navigator Auto-Make Log File-------------------------------------




Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file "D:/study/PCI/led.vhd" in Library work.ERROR:HDLParsers:164 - "D:/study/PCI/led.vhd" Line 36. parse error, unexpected CLOSEPAR, expecting IDENTIFIER--> Total memory usage is 77144 kilobytesNumber of errors   :    1 (   0 filtered)Number of warnings :    0 (   0 filtered)Number of infos    :    0 (   0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file "D:/study/PCI/led.vhd" in Library work.ERROR:HDLParsers:164 - "D:/study/PCI/led.vhd" Line 36. parse error, unexpected CLOSEPAR, expecting IDENTIFIER--> Total memory usage is 77144 kilobytesNumber of errors   :    1 (   0 filtered)Number of warnings :    0 (   0 filtered)Number of infos    :    0 (   0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file "D:/study/PCI/led.vhd" in Library work.Entity <led> compiled.Entity <led> (Architecture <Behavioral>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <led> (Architecture <Behavioral>).Entity <led> analyzed. Unit <led> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <led>.    Related source file is "D:/study/PCI/led.vhd".Unit <led> synthesized.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <led> ...

Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file "D:/study/PCI/led.vhd" in Library work.ERROR:HDLParsers:164 - "D:/study/PCI/led.vhd" Line 34. parse error, unexpected EQ, expecting SEMICOLON or CLOSEPAR--> Total memory usage is 77144 kilobytesNumber of errors   :    1 (   0 filtered)Number of warnings :    0 (   0 filtered)Number of infos    :    0 (   0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file "D:/study/PCI/led.vhd" in Library work.Entity <led> compiled.Entity <led> (Architecture <behavioral>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <led> (Architecture <behavioral>).Entity <led> analyzed. Unit <led> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <led>.    Related source file is "D:/study/PCI/led.vhd".WARNING:Xst:1306 - Output <led1> is never assigned.WARNING:Xst:1306 - Output <led2> is never assigned.Unit <led> synthesized.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <led> ...

Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file "D:/study/PCI/led.vhd" in Library work.Entity <led> compiled.Entity <led> (Architecture <behavioral>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <led> (Architecture <behavioral>).Entity <led> analyzed. Unit <led> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <led>.    Related source file is "D:/study/PCI/led.vhd".WARNING:Xst:1306 - Output <led1> is never assigned.WARNING:Xst:1306 - Output <led2> is never assigned.Unit <led> synthesized.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro================
12345

__projnav.log - 源码说明

本页面展示了「采用9054做为板卡与计算机通信的媒介」中的 __projnav.log 源码文件，采用 LOG 编程语言编写，共 1,812 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

虫虫下载站收录了大量与9054相关的技术资源，包括源代码、技术文档、电路图等，是电子工程师和嵌入式开发者的专业学习平台。

⌨️ 快捷键说明

复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?