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来自「采用9054做为板卡与计算机通信的媒介」· LOG 代码 · 共 1,812 行 · 第 1/5 页
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Started process "Fit".Release 7.1.04i - CPLD Optimizer/Partitioner H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Considering device XC95288XL-10-TQ144.Flattening design..Timing optimizationTiming driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 27 equations into 16 function blocks...........................................................................................................................................................................................................................................................................................................................................................Design a90541 has been optimized and fit into device XC95288XL-10-TQ144.
Started process "Generate Post-Fit Simulation Model".Release 7.1.04i - CPLD Timing Simulation Interface H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Creating NGA for simulation.Speed File: Version 3.0
Release 7.1.04i - netgen H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Command Line: netgen -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sima90541.nga a90541_timesim.vhd Reading design 'a90541.nga' ...Flattening design ...Processing design ... Preping design's networks ... Preping design's macros ...Writing VHDL netlist 'a90541_timesim.vhd' ...Writing VHDL SDF file 'a90541_timesim.sdf' ...INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx SIMPRIM simulation primitives and has to be used with SIMPRIM library for correct compilation and simulation. Number of warnings: 0Number of info messages: 1Total memory usage is 44204 kilobytesCreated netgen log file 'a90541_timesim.nlf'.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "D:/study/PCI/90541.vhd" in Library work.Entity <a90541> compiled.Entity <a90541> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <a90541> (Architecture <behavioral>).WARNING:Xst:819 - "D:/study/PCI/90541.vhd" line 144: The following signals are missing in the process sensitivity list: int.Entity <a90541> analyzed. Unit <a90541> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <a90541>. Related source file is "D:/study/PCI/90541.vhd".WARNING:Xst:647 - Input <la> is never used.WARNING:Xst:1778 - Inout <ld> is assigned but never used.WARNING:Xst:653 - Signal <reg> is used but never assigned. Tied to value 00000000. Register <int1> equivalent to <lint> has been removed Found 1-bit register for signal <lholda>. Found 1-bit register for signal <ready>. Found 1-bit register for signal <lint>. Found 8-bit tristate buffer for signal <ld>. Found 1-bit register for signal <we>. Found 1-bit register for signal <oe>. Found 1-bit register for signal <int>. Found 1-bit register for signal <int2>. Found 1-bit register for signal <int3>. Found 1-bit register for signal <int4>. Found 8-bit register for signal <Mtridata_ld> created at line 107. Found 1-bit register for signal <Mtrien_ld> created at line 107. Summary: inferred 8 D-type flip-flop(s). inferred 8 Tristate(s).Unit <a90541> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 11 1-bit register : 10 8-bit register : 1# Tristates : 1 8-bit tristate buffer : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================WARNING:Xst:1710 - FF/Latch <Mtridata_ld_7> (without init value) has a constant value of 0 in block <a90541>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Mtridata_ld_6> (without init value) has a constant value of 0 in block <a90541>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Mtridata_ld_0> (without init value) has a constant value of 0 in block <a90541>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Mtridata_ld_1> (without init value) has a constant value of 0 in block <a90541>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Mtridata_ld_2> (without init value) has a constant value of 0 in block <a90541>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Mtridata_ld_3> (without init value) has a constant value of 0 in block <a90541>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Mtridata_ld_4> (without init value) has a constant value of 0 in block <a90541>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Mtridata_ld_5> (without init value) has a constant value of 0 in block <a90541>.WARNING:Xst:638 - in unit a90541 Conflict on KEEP property on signal Mtridata_ld<7> and Mtridata_ld<6> Mtridata_ld<6> signal will be lost.WARNING:Xst:638 - in unit a90541 Conflict on KEEP property on signal Mtridata_ld<7> and Mtridata_ld<0> Mtridata_ld<0> signal will be lost.WARNING:Xst:638 - in unit a90541 Conflict on KEEP property on signal Mtridata_ld<7> and Mtridata_ld<1> Mtridata_ld<1> signal will be lost.WARNING:Xst:638 - in unit a90541 Conflict on KEEP property on signal Mtridata_ld<7> and Mtridata_ld<2> Mtridata_ld<2> signal will be lost.WARNING:Xst:638 - in unit a90541 Conflict on KEEP property on signal Mtridata_ld<7> and Mtridata_ld<3> Mtridata_ld<3> signal will be lost.WARNING:Xst:638 - in unit a90541 Conflict on KEEP property on signal Mtridata_ld<7> and Mtridata_ld<4> Mtridata_ld<4> signal will be lost.WARNING:Xst:638 - in unit a90541 Conflict on KEEP property on signal Mtridata_ld<7> and Mtridata_ld<5> Mtridata_ld<5> signal will be lost.Optimizing unit <a90541> ... implementation constraint: iob=auto : Mtridata_ld<7> implementation constraint: iob=auto : Mtrien_ld implementation constraint: KEEP : Mtrien_ld implementation constraint: INIT=s : ready implementation constraint: INIT=r : lholda
Started process "Translate".Release 7.1.04i - ngdbuild H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -i -p xc9500xl a90541.ngc a90541.ngd Reading NGO file 'D:/study/PCI/a90541.ngc' ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "a90541.ngd" ...Writing NGDBUILD log file "a90541.bld"...NGDBUILD done.
Started process "Fit".Release 7.1.04i - CPLD Optimizer/Partitioner H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Considering device XC95288XL-10-TQ144.Flattening design..Timing optimizationTiming driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 44 equations into 16 function blocks.......................................................................................................................................................................................................................................................................................................................................................................Design a90541 has been optimized and fit into device XC95288XL-10-TQ144.
Started process "Generate Post-Fit Simulation Model".Release 7.1.04i - CPLD Timing Simulation Interface H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Creating NGA for simulation.Speed File: Version 3.0
Release 7.1.04i - netgen H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Command Line: netgen -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sima90541.nga a90541_timesim.vhd Reading design 'a90541.nga' ...Flattening design ...Processing design ... Preping design's networks ... Preping design's macros ...Writing VHDL netlist 'a90541_timesim.vhd' ...Writing VHDL SDF file 'a90541_timesim.sdf' ...INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx SIMPRIM simulation primitives and has to be used with SIMPRIM library for correct compilation and simulation. Number of warnings: 0Number of info messages: 1Total memory usage is 44204 kilobytesCreated netgen log file 'a90541_timesim.nlf'.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "D:/study/PCI/90541.vhd" in Library work.Entity <a90541> compiled.Entity <a90541> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <a90541> (Architecture <behavioral>).WARNING:Xst:819 - "D:/study/PCI/90541.vhd" line 144: The following signals are missing in the process sensitivity list: int.Entity <a90541> analyzed. Unit <a90541> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <a90541>. Related source file is "D:/study/PCI/90541.vhd".WARNING:Xst:1778 - Inout <ld> is assigned but never used.WARNING:Xst:653 - Signal <reg> is used but never assigned. Tied to value 00000000. Register <int1> equivalent to <lint> has been removed Found 1-bit register for signal <lholda>. Found 1-bit register for signal <ready>. Found 1-bit register for signal <lint>. Found 8-bit tristate buffer for signal <ld>. Found 1-bit register for signal <we>. Found 1-bit register for signal <oe>. Found 1-bit register for signal <int>. Found 1-bit register for signal <int2>. Found 1-bit register for signal <int3>. Found 1-bit register for signal <int4>. Found 8-bit register for signal <Mtridata_ld> created at line 107. Found 1-bit register for signal <Mtrien_ld> created at line 107. Summary: inferred 8 D-type flip-flop(s). inferred 8 Tristate(s).Unit <a90541> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 11 1-bit register : 10 8-bit register : 1# Tristates : 1 8-bit tristate buffer : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================WARNING:Xst:1710 - FF/Latch <Mtridata_ld_7> (without init value) has a constant value of 0 in block <a90541>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Mtridata_ld_6> (without init value) has a constant value of 0 in block <a90541>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Mtridata_ld_0> (without init value) has a constant value of 0 in block <a90541>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Mtridata_ld_1> (without init value) has a constant value of 0 in block <a90541>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Mtridata_ld_2> (without init value) has a constant value of 0 in block <a90541>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Mtridata_ld_3> (without init value) has a constant value of 0 in block <a90541>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Mtridata_ld_4> (without init value) has a constant value of 0 in block <a90541>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Mtridata_ld_5> (without init value) has a constant value of 0 in block <a90541>.WARNING:Xst:638 - in unit a90541 Conflict on KEEP property on signal Mtridata_ld<7> and Mtridata_ld<6> Mtridata_ld<6> signal will be lost.WARNING:Xst:638 - in unit a90541 Conflict on KEEP property on signal Mtridata_ld<7> and Mtridata_ld<0> Mtridata_ld<0> signal will be lost.WARNING:Xst:638 - in unit a90541 Conflict on KEEP property on signal Mtridata_ld<7> and Mtridata_ld<1> Mtridata_ld<1> signal will be lost.WARNING:Xst:638 - in unit a90541 Conflict on KEEP property on signal Mtridata_ld<7> and Mtridata_ld<2> Mtridata_ld<2> signal will be lost.WARNING:Xst:638 - in unit a90541 Conflict on KEEP property on signal Mtridata_ld<7> and Mtridata_ld<3> Mtridata_ld<3> signal will be lost.WARNING:Xst:638 - in unit a90541 Conflict on KEEP property on signal Mtridata_ld<7> and Mtridata_ld<4> Mtridata_ld<4> signal will be lost.WARNING:Xst:638 - in unit a90541 Conflict on KEEP property on signal Mtridata_ld<7> and Mtridata_ld<5> Mtridata_ld<5> signal will be lost.Optimizing unit <a90541> ... implementation constraint: iob=auto : Mtridata_ld<7> implementation constraint: iob=auto : Mtrien_ld implementation constraint: KEEP : Mtrien_ld implementation constraint: INIT=s : ready implementation constraint: INIT=r : lholda
Started process "Translate".⌨️ 快捷键说明
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