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Preping design's networks ... Preping design's macros ...Writing VHDL netlist 'a90541_timesim.vhd' ...Writing VHDL SDF file 'a90541_timesim.sdf' ...INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx SIMPRIM simulation primitives and has to be used with SIMPRIM library for correct compilation and simulation. Number of warnings: 0Number of info messages: 1Total memory usage is 44204 kilobytesCreated netgen log file 'a90541_timesim.nlf'.
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "D:/study/PCI/90541.vhd" in Library work.Entity <a90541> compiled.Entity <a90541> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <a90541> (Architecture <behavioral>).INFO:Xst:1739 - HDL ADVISOR - "D:/study/PCI/90541.vhd" line 33: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.INFO:Xst:1739 - HDL ADVISOR - "D:/study/PCI/90541.vhd" line 35: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.INFO:Xst:1739 - HDL ADVISOR - "D:/study/PCI/90541.vhd" line 36: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.INFO:Xst:1739 - HDL ADVISOR - "D:/study/PCI/90541.vhd" line 41: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.INFO:Xst:1739 - HDL ADVISOR - "D:/study/PCI/90541.vhd" line 42: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.INFO:Xst:1739 - HDL ADVISOR - "D:/study/PCI/90541.vhd" line 44: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.INFO:Xst:1739 - HDL ADVISOR - "D:/study/PCI/90541.vhd" line 51: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.WARNING:Xst:819 - "D:/study/PCI/90541.vhd" line 141: The following signals are missing in the process sensitivity list: int.Entity <a90541> analyzed. Unit <a90541> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <a90541>. Related source file is "D:/study/PCI/90541.vhd".WARNING:Xst:647 - Input <la<3:0>> is never used. Register <int1> equivalent to <lint> has been removed Found 1-bit register for signal <lholda>. Found 1-bit register for signal <ready>. Found 1-bit register for signal <lint>. Found 8-bit tristate buffer for signal <ld>. Found 1-bit register for signal <we>. Found 1-bit register for signal <oe>. Found 4-bit tristate buffer for signal <sa<3:0>>. Found 1-bit register for signal <int>. Found 1-bit register for signal <int2>. Found 1-bit register for signal <int3>. Found 1-bit register for signal <int4>. Found 8-bit register for signal <Mtridata_ld> created at line 104. Found 1-bit register for signal <Mtrien_ld> created at line 104. Found 8-bit register for signal <reg>. Summary: inferred 8 D-type flip-flop(s). inferred 12 Tristate(s).Unit <a90541> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 12 1-bit register : 10 8-bit register : 2# Tristates : 5 1-bit tristate buffer : 4 8-bit tristate buffer : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <a90541> ... implementation constraint: iob=auto : Mtridata_ld<2> implementation constraint: iob=auto : Mtridata_ld<4> implementation constraint: iob=auto : Mtridata_ld<3> implementation constraint: iob=auto : Mtridata_ld<1> implementation constraint: iob=auto : Mtridata_ld<0> implementation constraint: iob=auto : Mtrien_ld implementation constraint: KEEP : Mtrien_ld implementation constraint: iob=auto : Mtridata_ld<7> implementation constraint: iob=auto : Mtridata_ld<6> implementation constraint: iob=auto : Mtridata_ld<5> implementation constraint: INIT=s : ready implementation constraint: INIT=r : lholda
Started process "Translate".Release 7.1.04i - ngdbuild H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -i -p xc9500xl a90541.ngc a90541.ngd Reading NGO file 'D:/study/PCI/a90541.ngc' ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "a90541.ngd" ...Writing NGDBUILD log file "a90541.bld"...NGDBUILD done.
Started process "Fit".Release 7.1.04i - CPLD Optimizer/Partitioner H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Considering device XC95288XL-10-TQ144.Flattening design..Timing optimization.......Timing driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 45 equations into 16 function blocks..........................................................................................................................................................................................................................................................................................................................................................................................................................................Design a90541 has been optimized and fit into device XC95288XL-10-TQ144.
Started process "Generate Post-Fit Simulation Model".Release 7.1.04i - CPLD Timing Simulation Interface H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Creating NGA for simulation.Speed File: Version 3.0
Release 7.1.04i - netgen H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Command Line: netgen -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sima90541.nga a90541_timesim.vhd Reading design 'a90541.nga' ...Flattening design ...Processing design ... Preping design's networks ... Preping design's macros ...Writing VHDL netlist 'a90541_timesim.vhd' ...Writing VHDL SDF file 'a90541_timesim.sdf' ...INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx SIMPRIM simulation primitives and has to be used with SIMPRIM library for correct compilation and simulation. Number of warnings: 0Number of info messages: 1Total memory usage is 44204 kilobytesCreated netgen log file 'a90541_timesim.nlf'.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "D:/study/PCI/90541.vhd" in Library work.Entity <a90541> compiled.ERROR:HDLParsers:1401 - "D:/study/PCI/90541.vhd" Line 63. Object lclk of mode OUT can not be read.ERROR:HDLParsers:1411 - "D:/study/PCI/90541.vhd" Line 68. Parameter lint of mode out can not be associated with a formal parameter of mode in.ERROR:HDLParsers:1411 - "D:/study/PCI/90541.vhd" Line 69. Parameter ready of mode out can not be associated with a formal parameter of mode in.ERROR:HDLParsers:1401 - "D:/study/PCI/90541.vhd" Line 70. Object lclk of mode OUT can not be read.ERROR:HDLParsers:1413 - "D:/study/PCI/90541.vhd" Line 72. Attribute event of output object lclk can not be read.ERROR:HDLParsers:1401 - "D:/study/PCI/90541.vhd" Line 72. Object lclk of mode OUT can not be read.WARNING:HDLParsers:1406 - "D:/study/PCI/90541.vhd" Line 70. No sensitivity list and no wait in the processERROR:HDLParsers:1401 - "D:/study/PCI/90541.vhd" Line 83. Object lclk of mode OUT can not be read.ERROR:HDLParsers:1413 - "D:/study/PCI/90541.vhd" Line 85. Attribute event of output object lclk can not be read.ERROR:HDLParsers:1401 - "D:/study/PCI/90541.vhd" Line 85. Object lclk of mode OUT can not be read.WARNING:HDLParsers:1406 - "D:/study/PCI/90541.vhd" Line 83. No sensitivity list and no wait in the processERROR:HDLParsers:1401 - "D:/study/PCI/90541.vhd" Line 98. Object lclk of mode OUT can not be read.ERROR:HDLParsers:1401 - "D:/study/PCI/90541.vhd" Line 110. Object ready of mode OUT can not be read.ERROR:HDLParsers:1413 - "D:/study/PCI/90541.vhd" Line 100. Attribute event of output object lclk can not be read.ERROR:HDLParsers:1401 - "D:/study/PCI/90541.vhd" Line 100. Object lclk of mode OUT can not be read.WARNING:HDLParsers:1406 - "D:/study/PCI/90541.vhd" Line 98. No sensitivity list and no wait in the processERROR:HDLParsers:1401 - "D:/study/PCI/90541.vhd" Line 124. Object lclk of mode OUT can not be read.ERROR:HDLParsers:1413 - "D:/study/PCI/90541.vhd" Line 126. Attribute event of output object lclk can not be read.ERROR:HDLParsers:1401 - "D:/study/PCI/90541.vhd" Line 126. Object lclk of mode OUT can not be read.WARNING:HDLParsers:1406 - "D:/study/PCI/90541.vhd" Line 124. No sensitivity list and no wait in the process--> Total memory usage is 77144 kilobytesNumber of errors : 16 ( 0 filtered)Number of warnings : 4 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "D:/study/PCI/90541.vhd" in Library work.Entity <a90541> compiled.ERROR:HDLParsers:1411 - "D:/study/PCI/90541.vhd" Line 68. Parameter lint of mode out can not be associated with a formal parameter of mode in.ERROR:HDLParsers:1411 - "D:/study/PCI/90541.vhd" Line 69. Parameter ready of mode out can not be associated with a formal parameter of mode in.ERROR:HDLParsers:1401 - "D:/study/PCI/90541.vhd" Line 110. Object ready of mode OUT can not be read.--> Total memory usage is 77144 kilobytesNumber of errors : 3 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *⌨️ 快捷键说明
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