pci.gfl

采用9054做为板卡与计算机通信的媒介

# XST (Creating Lso File) : 
90541.lso
# xst flow : RunXST
90541.syr
90541.prj
90541.sprj
90541.ana
90541.stx
90541.cmd_log
# XST (Creating Lso File) : 
90541.lso
# xst flow : RunXST
90541.syr
90541.prj
90541.sprj
90541.ana
90541.stx
90541.cmd_log
# XST (Creating Lso File) : 
90541.lso
# xst flow : RunXST
90541.syr
90541.prj
90541.sprj
90541.ana
90541.stx
90541.cmd_log
# XST (Creating Lso File) : 
90541.lso
# xst flow : RunXST
90541.syr
90541.prj
90541.sprj
90541.ana
90541.stx
90541.cmd_log
# XST (Creating Lso File) : 
a90541.lso
# xst flow : RunXST
a90541.syr
a90541.prj
a90541.sprj
a90541.ana
a90541.stx
a90541.cmd_log
# XST (Creating Lso File) : 
a90541.lso
# xst flow : RunXST
a90541.syr
a90541.prj
a90541.sprj
a90541.ana
a90541.stx
a90541.cmd_log
a90541.ngc
a90541.ngr
# Bencher : Creating project file
ss_bencher.prj
# ProjNav -> New Source -> TBW
ss.vhw
ss.ano
ss.tfw
ss.ant
# Bencher : Creating project file
ss_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
ss_bencher.prj
# Bencher : Creating project file
ss_bencher.prj
# Bencher : Creating project file
ss_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
ss.vhw
ss.ano
ss.tfw
ss.ant
# ModelSim : Simulate Behavioral VHDL Model
ss.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Implmentation : Translate (CPLD flow)
__projnav/a90541_edfTOngd_tcl.rsp
a90541.ngd
a90541.bld
a90541_ngdbuild.nav
_ngo/netlist.lst
.untf
a90541_html
a90541.cmd_log
# Implmentation : Fit
__projnav/a90541_ngdTOvm6_tcl.rsp
a90541.vm6
a90541.cxt
a90541.blx
a90541.mfd
a90541.rpt
a90541.log
a90541.pnx
a90541.gyd
a90541.xml
a90541_build.xml
PCI.ptf
a90541.bl
errors.xml
tmperr.err
a90541.cmd_log
# Generate Post-Fit Simulation Model
__projnav/a90541_vm6TOnga_tcl.rsp
a90541.nga
a90541.cmd_log
# Implmentation : Generate Post-Par Simulation Model (VHDL flow)
a90541_timesim.vhd
a90541_timesim.vhd
ngaTOa90541.vhdsim_par
a90541.vhdsim_par
a90541_timesim.nlf
a90541.cmd_log
# Bencher : Creating project file
ss_bencher.prj
# Hidden Remap : Simulate Post-Place & Route VHDL Model
ss.timesim_vhw
_remap.tmp
# ModelSim : Simulate Post-Place & Route VHDL Model
ss.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
ss_bencher.prj
# Bencher : Creating project file
jj_bencher.prj
# ProjNav -> New Source -> TBW
jj.vhw
jj.ano
jj.tfw
jj.ant
# Bencher : Creating project file
jj_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
jj_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
jj.vhw
jj.ano
jj.tfw
jj.ant
# ModelSim : Simulate Behavioral VHDL Model
jj.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
jj.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
jj_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
jj_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
jj.vhw
jj.ano
jj.tfw
jj.ant
# ModelSim : Simulate Behavioral VHDL Model
jj.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
jj.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
jj.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Bencher : Creating project file
jj_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# XST (Creating Lso File) : 
a90541.lso
# xst flow : RunXST
a90541.syr
a90541.prj
a90541.sprj
a90541.ana
a90541.stx
a90541.cmd_log
a90541.ngc
a90541.ngr
# Implmentation : Translate (CPLD flow)
__projnav/a90541_edfTOngd_tcl.rsp
a90541.ngd
a90541.bld
a90541_ngdbuild.nav
_ngo/netlist.lst
.untf
a90541_html
a90541.cmd_log
# Implmentation : Fit
__projnav/a90541_ngdTOvm6_tcl.rsp
a90541.vm6
a90541.cxt
a90541.blx
a90541.mfd
a90541.rpt
a90541.log
a90541.pnx
a90541.gyd
a90541.xml
a90541_build.xml
PCI.ptf
a90541.bl
errors.xml
tmperr.err
a90541.cmd_log
# Generate Post-Fit Simulation Model
__projnav/a90541_vm6TOnga_tcl.rsp
a90541.nga
a90541.cmd_log
# Implmentation : Generate Post-Par Simulation Model (VHDL flow)
a90541_timesim.vhd
a90541_timesim.vhd
ngaTOa90541.vhdsim_par
a90541.vhdsim_par
a90541_timesim.nlf
a90541.cmd_log
# Bencher : Creating project file
jj_bencher.prj
# Hidden Remap : Simulate Post-Place & Route VHDL Model
jj.timesim_vhw
_remap.tmp
# ModelSim : Simulate Post-Place & Route VHDL Model
jj.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher : Creating project file
jj_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
jj.vhw
jj.ano
jj.tfw
jj.ant
# XST (Creating Lso File) : 
a90541.lso
# xst flow : RunXST
a90541.syr
a90541.prj
a90541.sprj
a90541.ana
a90541.stx
a90541.cmd_log
a90541.ngc
a90541.ngr
# Bencher : Creating project file
jj_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
jj.vhw
jj.ano
jj.tfw
jj.ant
# XST (Creating Lso File) : 
a90541.lso
# xst flow : RunXST
a90541.syr
a90541.prj
a90541.sprj
a90541.ana
a90541.stx
a90541.cmd_log
a90541.ngc
a90541.ngr
# Bencher : Creating project file
jj_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
jj.vhw
jj.ano
jj.tfw
jj.ant
# XST (Creating Lso File) : 
a90541.lso
# xst flow : RunXST
a90541.syr
a90541.prj
a90541.sprj
a90541.ana
a90541.stx
a90541.cmd_log
a90541.ngc
a90541.ngr
# Bencher : Creating project file
jj_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
jj.vhw
jj.ano
jj.tfw
jj.ant
# XST (Creating Lso File) : 
a90541.lso
# xst flow : RunXST
a90541.syr
a90541.prj
a90541.sprj
a90541.ana
a90541.stx
a90541.cmd_log
a90541.ngc
a90541.ngr
# Implmentation : Translate (CPLD flow)
__projnav/a90541_edfTOngd_tcl.rsp
a90541.ngd
a90541.bld
a90541_ngdbuild.nav
_ngo/netlist.lst
.untf
a90541_html
a90541.cmd_log
# Implmentation : Fit
__projnav/a90541_ngdTOvm6_tcl.rsp
a90541.vm6
a90541.cxt
a90541.blx
a90541.mfd
a90541.rpt
a90541.log
a90541.pnx
a90541.gyd
a90541.xml
a90541_build.xml
PCI.ptf
a90541.bl
errors.xml
tmperr.err
a90541.cmd_log
# Generate Post-Fit Simulation Model
__projnav/a90541_vm6TOnga_tcl.rsp
a90541.nga
a90541.cmd_log
# Implmentation : Generate Post-Par Simulation Model (VHDL flow)
a90541_timesim.vhd
a90541_timesim.vhd
ngaTOa90541.vhdsim_par
a90541.vhdsim_par
a90541_timesim.nlf
a90541.cmd_log
# Bencher : Creating project file
jj_bencher.prj
# Hidden Remap : Simulate Post-Place & Route VHDL Model
jj.timesim_vhw
_remap.tmp
# ModelSim : Simulate Post-Place & Route VHDL Model
jj.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher : Creating project file
ss_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
ss_bencher.prj
# ProjNav -> New Source -> TBW
ss.vhw
ss.ano
ss.tfw
ss.ant
# Bencher : Creating project file
ss_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
ss_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
ss.vhw
ss.ano
ss.tfw
ss.ant
# Bencher : Creating project file
ss_bencher.prj
# Hidden Remap : Simulate Post-Place & Route VHDL Model
ss.timesim_vhw
_remap.tmp
# ModelSim : Simulate Post-Place & Route VHDL Model
ss.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher : Creating project file
ss_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
ss.vhw
ss.ano
ss.tfw
ss.ant
# XST (Creating Lso File) : 
a90541.lso
# xst flow : RunXST
a90541.syr
a90541.prj
a90541.sprj
a90541.ana
a90541.stx
a90541.cmd_log
a90541.ngc
a90541.ngr
# Implmentation : Translate (CPLD flow)
__projnav/a90541_edfTOngd_tcl.rsp
a90541.ngd
a90541.bld
a90541_ngdbuild.nav
_ngo/netlist.lst
.untf
a90541_html
a90541.cmd_log
# Implmentation : Fit
__projnav/a90541_ngdTOvm6_tcl.rsp
a90541.vm6
a90541.cxt
a90541.blx
a90541.mfd
a90541.rpt
a90541.log
a90541.pnx
a90541.gyd
a90541.xml
a90541_build.xml
PCI.ptf
a90541.bl
errors.xml
tmperr.err
a90541.cmd_log
# Generate Post-Fit Simulation Model
__projnav/a90541_vm6TOnga_tcl.rsp
a90541.nga
a90541.cmd_log
# Implmentation : Generate Post-Par Simulation Model (VHDL flow)
a90541_timesim.vhd
a90541_timesim.vhd
ngaTOa90541.vhdsim_par
a90541.vhdsim_par
a90541_timesim.nlf
a90541.cmd_log
# Bencher : Creating project file
ss_bencher.prj
# Hidden Remap : Simulate Post-Place & Route VHDL Model
ss.timesim_vhw
_remap.tmp
# ModelSim : Simulate Post-Place & Route VHDL Model
ss.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher : Creating project file
ss_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
ss.vhw
ss.ano
ss.tfw
ss.ant
# XST (Creating Lso File) : 
a90541.lso
# xst flow : RunXST
a90541.syr
a90541.prj
a90541.sprj
a90541.ana
a90541.stx
a90541.cmd_log
a90541.ngc
a90541.ngr
# Implmentation : Translate (CPLD flow)
__projnav/a90541_edfTOngd_tcl.rsp
a90541.ngd
a90541.bld
a90541_ngdbuild.nav
_ngo/netlist.lst
.untf
a90541_html
a90541.cmd_log
# Implmentation : Fit
__projnav/a90541_ngdTOvm6_tcl.rsp
a90541.vm6
a90541.cxt
a90541.blx
a90541.mfd
a90541.rpt
a90541.log
a90541.pnx
a90541.gyd
a90541.xml
a90541_build.xml
PCI.ptf
a90541.bl
errors.xml
tmperr.err
a90541.cmd_log
# Generate Post-Fit Simulation Model
__projnav/a90541_vm6TOnga_tcl.rsp
a90541.nga
a90541.cmd_log
# Implmentation : Generate Post-Par Simulation Model (VHDL flow)
a90541_timesim.vhd
a90541_timesim.vhd
ngaTOa90541.vhdsim_par
a90541.vhdsim_par
a90541_timesim.nlf
a90541.cmd_log
# Bencher : Creating project file
ss_bencher.prj
# Hidden Remap : Simulate Post-Place & Route VHDL Model
ss.timesim_vhw
_remap.tmp
# ModelSim : Simulate Post-Place & Route VHDL Model
ss.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher : Creating project file
ss_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
ss.vhw
ss.ano
ss.tfw
ss.ant
# XST (Creating Lso File) : 
a90541.lso
# xst flow : RunXST
a90541.syr
a90541.prj
a90541.sprj
a90541.ana
a90541.stx
a90541.cmd_log
a90541.ngc
a90541.ngr
# Implmentation : Translate (CPLD flow)
__projnav/a90541_edfTOngd_tcl.rsp
a90541.ngd
a90541.bld
a90541_ngdbuild.nav
_ngo/netlist.lst
.untf
a90541_html
a90541.cmd_log
# Implmentation : Fit
__projnav/a90541_ngdTOvm6_tcl.rsp
a90541.vm6
a90541.cxt
a90541.blx
a90541.mfd
a90541.rpt
a90541.log
a90541.pnx
a90541.gyd
a90541.xml
a90541_build.xml
PCI.ptf
a90541.bl
errors.xml
tmperr.err
a90541.cmd_log
# Generate Post-Fit Simulation Model
__projnav/a90541_vm6TOnga_tcl.rsp
a90541.nga
a90541.cmd_log
# Implmentation : Generate Post-Par Simulation Model (VHDL flow)
a90541_timesim.vhd
a90541_timesim.vhd
ngaTOa90541.vhdsim_par
a90541.vhdsim_par
a90541_timesim.nlf
a90541.cmd_log
# Bencher : Creating project file
ss_bencher.prj
# Hidden Remap : Simulate Post-Place & Route VHDL Model
ss.timesim_vhw
_remap.tmp
# ModelSim : Simulate Post-Place & Route VHDL Model
ss.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher : Creating project file
jj_bencher.prj
# Bencher : Creating project file
ss_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
ss_bencher.prj
# Hidden Remap : Simulate Post-Place & Route VHDL Model
ss.timesim_vhw
_remap.tmp
# ModelSim : Simulate Post-Place & Route VHDL Model
ss.tdo
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# Bencher : Creating project file
ss_bencher.prj
# ModelSim : Simulate Post-Place & Route VHDL Model
vsim.wlf
# XST (Creating Lso File) : 
led.lso
# xst flow : RunXST
led.syr
led.prj
led.sprj
led.ana
led.stx
led.cmd_log
# XST (Creating Lso File) : 
led.lso
# xst flow : RunXST
led.syr
led.prj
led.sprj
led.ana
led.stx
led.cmd_log
# XST (Creating Lso File) : 
led.lso
# xst flow : RunXST
led.syr
led.prj
led.sprj
led.ana
led.stx
led.cmd_log
led.ngc
led.ngr
# Bencher : Creating project file
led1_bencher.prj
# ProjNav -> New Source -> TBW
led1.vhw
led1.ano
led1.tfw
led1.ant
# XST (Creating Lso File) : 
led.lso
# xst flow : RunXST
led.syr
led.prj
led.sprj
led.ana
led.stx
led.cmd_log
led.ngc
led.ngr
# XST (Creating Lso File) : 
led.lso
# xst flow : RunXST
led.syr
led.prj
led.sprj
led.ana
led.stx
led.cmd_log
led.ngc
led.ngr
# Bencher : Creating project file
led2_bencher.prj
# ProjNav -> New Source -> TBW
led2.vhw
led2.ano
led2.tfw
led2.ant
# XST (Creating Lso File) : 
led.lso
# xst flow : RunXST
led.syr
led.prj
led.sprj
led.ana
led.stx
led.cmd_log
led.ngc
led.ngr
# Bencher : Creating project file
led1_bencher.prj
# ProjNav -> New Source -> TBW
led1.vhw
led1.ano
led1.tfw
led1.ant
# Bencher : Creating project file
led1_bencher.prj
# Bencher Waveform : PDCL (jhdparse)
# Bencher : Creating project file
led1_bencher.prj
# Update Bencher Waveform
__projnav/updateTBW_tcl.rsp
led1.vhw
led1.ano
led1.tfw
led1.ant
# Implmentation : Translate (CPLD flow)
__projnav/led_edfTOngd_tcl.rsp
led.ngd
led.bld
led_ngdbuild.nav
_ngo/netlist.lst
.untf
led_html
led.cmd_log
# Implmentation : Fit
__projnav/led_ngdTOvm6_tcl.rsp
led.vm6
led.cxt
led.blx
led.mfd
led.rpt
led.log
led.pnx
led.gyd
led.xml
led_build.xml