jj.ant

来自「采用9054做为板卡与计算机通信的媒介」· ANT 代码 · 共 240 行

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 7.1.04i
--  \   \         Application : ISE Foundation
--  /   /         Filename : jj.ant
-- /___/   /\     Timestamp : Thu Mar 15 20:02:57 2007
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: jj
--Device: Xilinx
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY jj IS
END jj;

ARCHITECTURE testbench_arch OF jj IS
    FILE RESULTS: TEXT OPEN WRITE_MODE IS "D:\study\PCI\jj.ano";

    COMPONENT a90541
        PORT (
            main_clk : In std_logic;
            lholda : Buffer std_logic;
            lhold : In std_logic;
            lclk : Buffer std_logic;
            ready : Buffer std_logic;
            blast : In std_logic;
            wr : In std_logic;
            ads : In std_logic;
            cpld : In std_logic;
            led1 : Buffer std_logic;
            led2 : Buffer std_logic;
            led : Out std_logic_vector (7 DownTo 0);
            lint : Buffer std_logic;
            ld : InOut std_logic_vector (7 DownTo 0);
            la : In std_logic_vector (14 DownTo 0);
            ce : Out std_logic;
            we : Out std_logic;
            oe : Out std_logic;
            onoffa : In std_logic;
            sa : Buffer std_logic_vector (14 DownTo 0)
        );
    END COMPONENT;

    SIGNAL main_clk : std_logic := '0';
    SIGNAL lholda : std_logic := '0';
    SIGNAL lhold : std_logic := '0';
    SIGNAL lclk : std_logic := '0';
    SIGNAL ready : std_logic := '0';
    SIGNAL blast : std_logic := '1';
    SIGNAL wr : std_logic := '0';
    SIGNAL ads : std_logic := '1';
    SIGNAL cpld : std_logic := '0';
    SIGNAL led1 : std_logic := '0';
    SIGNAL led2 : std_logic := '0';
    SIGNAL led : std_logic_vector (7 DownTo 0) := "00000000";
    SIGNAL lint : std_logic := '0';
    SIGNAL ld : std_logic_vector (7 DownTo 0) := "00000000";
    SIGNAL la : std_logic_vector (14 DownTo 0) := "000000000000000";
    SIGNAL ce : std_logic := '0';
    SIGNAL we : std_logic := '0';
    SIGNAL oe : std_logic := '0';
    SIGNAL onoffa : std_logic := '0';
    SIGNAL sa : std_logic_vector (14 DownTo 0) := "000000000000000";

    SHARED VARIABLE TX_ERROR : INTEGER := 0;
    SHARED VARIABLE TX_OUT : LINE;

    constant PERIOD : time := 100 ns;
    constant DUTY_CYCLE : real := 0.5;
    constant OFFSET : time := 0 ns;

    BEGIN
        UUT : a90541
        PORT MAP (
            main_clk => main_clk,
            lholda => lholda,
            lhold => lhold,
            lclk => lclk,
            ready => ready,
            blast => blast,
            wr => wr,
            ads => ads,
            cpld => cpld,
            led1 => led1,
            led2 => led2,
            led => led,
            lint => lint,
            ld => ld,
            la => la,
            ce => ce,
            we => we,
            oe => oe,
            onoffa => onoffa,
            sa => sa
        );

        PROCESS    -- clock process for main_clk
        BEGIN
            WAIT for OFFSET;
            CLOCK_LOOP : LOOP
                main_clk <= '0';
                WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
                main_clk <= '1';
                WAIT FOR (PERIOD * DUTY_CYCLE);
            END LOOP CLOCK_LOOP;
        END PROCESS;

        PROCESS    -- Annotation process for main_clk
            VARIABLE TX_TIME : INTEGER := 0;

            PROCEDURE ANNOTATE_led(
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
            BEGIN
                STD.TEXTIO.write(TX_LOC, string'("Annotate["));
                STD.TEXTIO.write(TX_LOC, TX_TIME);
                STD.TEXTIO.write(TX_LOC, string'(", led, "));
                IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, led);
                STD.TEXTIO.write(TX_LOC, string'("]"));
                TX_STR(TX_LOC.all'range) := TX_LOC.all;
                STD.TEXTIO.writeline(RESULTS, TX_LOC);
                STD.TEXTIO.Deallocate(TX_LOC);
            END;
            PROCEDURE ANNOTATE_ce(
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
            BEGIN
                STD.TEXTIO.write(TX_LOC, string'("Annotate["));
                STD.TEXTIO.write(TX_LOC, TX_TIME);
                STD.TEXTIO.write(TX_LOC, string'(", ce, "));
                IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, ce);
                STD.TEXTIO.write(TX_LOC, string'("]"));
                TX_STR(TX_LOC.all'range) := TX_LOC.all;
                STD.TEXTIO.writeline(RESULTS, TX_LOC);
                STD.TEXTIO.Deallocate(TX_LOC);
            END;
            PROCEDURE ANNOTATE_we(
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
            BEGIN
                STD.TEXTIO.write(TX_LOC, string'("Annotate["));
                STD.TEXTIO.write(TX_LOC, TX_TIME);
                STD.TEXTIO.write(TX_LOC, string'(", we, "));
                IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, we);
                STD.TEXTIO.write(TX_LOC, string'("]"));
                TX_STR(TX_LOC.all'range) := TX_LOC.all;
                STD.TEXTIO.writeline(RESULTS, TX_LOC);
                STD.TEXTIO.Deallocate(TX_LOC);
            END;
            PROCEDURE ANNOTATE_oe(
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
            BEGIN
                STD.TEXTIO.write(TX_LOC, string'("Annotate["));
                STD.TEXTIO.write(TX_LOC, TX_TIME);
                STD.TEXTIO.write(TX_LOC, string'(", oe, "));
                IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, oe);
                STD.TEXTIO.write(TX_LOC, string'("]"));
                TX_STR(TX_LOC.all'range) := TX_LOC.all;
                STD.TEXTIO.writeline(RESULTS, TX_LOC);
                STD.TEXTIO.Deallocate(TX_LOC);
            END;
        BEGIN
            WAIT for 1 fs;
            ANNOTATE_led(0);
            ANNOTATE_ce(0);
            ANNOTATE_we(0);
            ANNOTATE_oe(0);
            WAIT for OFFSET;
            TX_TIME := TX_TIME + 0;
            ANNO_LOOP : LOOP
                --Rising Edge
                WAIT for 65 ns;
                TX_TIME := TX_TIME + 65;
                ANNOTATE_led(TX_TIME);
                ANNOTATE_ce(TX_TIME);
                ANNOTATE_we(TX_TIME);
                ANNOTATE_oe(TX_TIME);
                WAIT for 35 ns;
                TX_TIME := TX_TIME + 35;
            END LOOP ANNO_LOOP;
        END PROCESS;

        PROCESS
            BEGIN
                -- -------------  Current Time:  235ns
                WAIT FOR 235 ns;
                lhold <= '1';
                -- -------------------------------------
                -- -------------  Current Time:  435ns
                WAIT FOR 200 ns;
                ads <= '0';
                -- -------------------------------------
                -- -------------  Current Time:  535ns
                WAIT FOR 100 ns;
                blast <= '0';
                ads <= '1';
                -- -------------------------------------
                -- -------------  Current Time:  635ns
                WAIT FOR 100 ns;
                blast <= '1';
                -- -------------------------------------
                -- -------------  Current Time:  735ns
                WAIT FOR 100 ns;
                lhold <= '0';
                -- -------------------------------------
                WAIT FOR 1365 ns;

                STD.TEXTIO.write(TX_OUT, string'("Total[]"));
                STD.TEXTIO.writeline(RESULTS, TX_OUT);
                ASSERT (FALSE) REPORT
                    "Success! Simulation for annotation completed"
                    SEVERITY FAILURE;
            END PROCESS;

    END testbench_arch;