a90541.syr

采用9054做为板卡与计算机通信的媒介

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 1.69 s | Elapsed : 0.00 / 2.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 1.69 s | Elapsed : 0.00 / 2.00 s
 
--> Reading design: a90541.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "a90541.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "a90541"
Output Format                      : NGC
Target Device                      : xc9500xl

---- Source Options
Top Module Name                    : a90541
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain

---- Other Options
lso                                : a90541.lso
verilog2001                        : YES
safe_implementation                : No
Clock Enable                       : YES
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/study/PCI/90541.vhd" in Library work.
Architecture behavioral of Entity a90541 is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <a90541> (Architecture <behavioral>).
WARNING:Xst:819 - "D:/study/PCI/90541.vhd" line 144: The following signals are missing in the process sensitivity list:
   int.
Entity <a90541> analyzed. Unit <a90541> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <a90541>.
    Related source file is "D:/study/PCI/90541.vhd".
WARNING:Xst:1778 - Inout <ld> is assigned but never used.
WARNING:Xst:653 - Signal <reg> is used but never assigned. Tied to value 00000000.
    Register <int1> equivalent to <lint> has been removed
    Found 1-bit register for signal <lholda>.
    Found 1-bit register for signal <ready>.
    Found 1-bit register for signal <lint>.
    Found 8-bit tristate buffer for signal <ld>.
    Found 1-bit register for signal <we>.
    Found 1-bit register for signal <oe>.
    Found 1-bit register for signal <int>.
    Found 1-bit register for signal <int2>.
    Found 1-bit register for signal <int3>.
    Found 1-bit register for signal <int4>.
    Found 8-bit register for signal <Mtridata_ld> created at line 107.
    Found 1-bit register for signal <Mtrien_ld> created at line 107.
    Summary:
	inferred   8 D-type flip-flop(s).
	inferred   8 Tristate(s).
Unit <a90541> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 11
 1-bit register                    : 10
 8-bit register                    : 1
# Tristates                        : 1
 8-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <Mtridata_ld_7> (without init value) has a constant value of 0 in block <a90541>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <Mtridata_ld_6> (without init value) has a constant value of 0 in block <a90541>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <Mtridata_ld_0> (without init value) has a constant value of 0 in block <a90541>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <Mtridata_ld_1> (without init value) has a constant value of 0 in block <a90541>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <Mtridata_ld_2> (without init value) has a constant value of 0 in block <a90541>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <Mtridata_ld_3> (without init value) has a constant value of 0 in block <a90541>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <Mtridata_ld_4> (without init value) has a constant value of 0 in block <a90541>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <Mtridata_ld_5> (without init value) has a constant value of 0 in block <a90541>.
WARNING:Xst:638 - in unit a90541 Conflict on KEEP property on signal Mtridata_ld<7> and Mtridata_ld<6> Mtridata_ld<6> signal will be lost.
WARNING:Xst:638 - in unit a90541 Conflict on KEEP property on signal Mtridata_ld<7> and Mtridata_ld<0> Mtridata_ld<0> signal will be lost.
WARNING:Xst:638 - in unit a90541 Conflict on KEEP property on signal Mtridata_ld<7> and Mtridata_ld<1> Mtridata_ld<1> signal will be lost.
WARNING:Xst:638 - in unit a90541 Conflict on KEEP property on signal Mtridata_ld<7> and Mtridata_ld<2> Mtridata_ld<2> signal will be lost.
WARNING:Xst:638 - in unit a90541 Conflict on KEEP property on signal Mtridata_ld<7> and Mtridata_ld<3> Mtridata_ld<3> signal will be lost.
WARNING:Xst:638 - in unit a90541 Conflict on KEEP property on signal Mtridata_ld<7> and Mtridata_ld<4> Mtridata_ld<4> signal will be lost.
WARNING:Xst:638 - in unit a90541 Conflict on KEEP property on signal Mtridata_ld<7> and Mtridata_ld<5> Mtridata_ld<5> signal will be lost.

Optimizing unit <a90541> ...
  implementation constraint: iob=auto	 : Mtridata_ld<7>
  implementation constraint: iob=auto	 : Mtrien_ld
  implementation constraint: KEEP	 : Mtrien_ld
  implementation constraint: INIT=s	 : ready
  implementation constraint: INIT=r	 : lholda

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : a90541.ngr
Top Level Output File Name         : a90541
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : YES
Target Technology                  : xc9500xl
Macro Preserve                     : YES
XOR Preserve                       : YES
Clock Enable                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 62

Macro Statistics :
# Registers                        : 8
#      1-bit register              : 8
# Tristates                        : 1
#      8-bit tristate buffer       : 1

Cell Usage :
# BELS                             : 15
#      AND2                        : 3
#      GND                         : 1
#      INV                         : 10
#      VCC                         : 1
# FlipFlops/Latches                : 10
#      FD                          : 5
#      FDC                         : 1
#      FDCE                        : 4
# IO Buffers                       : 62
#      IBUF                        : 22
#      OBUF                        : 32
#      OBUFE                       : 8
=========================================================================
CPU : 3.95 / 5.69 s | Elapsed : 4.00 / 6.00 s
 
--> 

Total memory usage is 79612 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   18 (   0 filtered)
Number of infos    :    0 (   0 filtered)