90541.vhd

来自「采用9054做为板卡与计算机通信的媒介」· VHDL 代码 · 共 156 行

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-- Company: 
-- Engineer:
--
-- Create Date:    18:54:50 03/15/07
-- Design Name:    
-- Module Name:    90541 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity a90541 is
 port (
        main_clk: in STD_LOGIC;
        lholda: out  STD_LOGIC:='0';
        lhold: in STD_LOGIC;
        lclk: out STD_LOGIC;
       ready: out STD_LOGIC:='1';
       blast: in std_logic;
        wr: in STD_LOGIC;
        ads:in STD_LOGIC;
        cpld:in STD_LOGIC;
        led1: out STD_LOGIC;
        led2: out STD_LOGIC;
        led:out std_logic_vector(7 downto 0);
        lint:out std_logic;
        ld: inout std_logic_vector(7 downto 0);
         la: in STD_LOGIC_VECTOR (14 downto 0);
         ce:out STD_LOGIC;
         we:out std_logic;
         oe:out std_logic;
         onoffa:in std_logic;
         sa:out std_logic_vector(14 downto 0)
          );

end a90541;

architecture Behavioral of a90541 is
 signal reg:std_logic_vector(7 downto 0);
	signal int,int1,int2,int3,int4,regclk:std_logic;


begin
ce <= '0';
led2 <= '1';
lclk<= main_clk;
         		regclk<=main_clk;
         		led<=reg;
					sa <= la;
--         		sa(14 downto 4)<=la(14 downto 4);
--         		sa(3 downto 0)<="ZZZZ";
         		led1<=onoffa;
--         		led2<= not lint;
--         		ce<=ready or regclk or cpld;
 	process(regclk)
	begin
  		if(regclk'event and regclk='1') 
  		then 
  			if(lhold='1') 
  			then
     				lholda<=  '1' ;--after 5 ns;
     			else
       				lholda<='0'; --after 5 ns;
     			end if;
  		end if;
 	end process;                                    
   
  	process(regclk)
  	begin
    		if(regclk'event and regclk='1') 
    		then
    			if(ads='0')
    			then
    				ready<='0';
    			end if;
    			if(blast='0')
    			then
    				ready<='1';
    			end if;
    		end if;
        			
 	end process;
 	process(regclk)
 	begin
       		if(regclk'event and regclk='1')
      	         	then
      	         		if(cpld='0')
      	         		then
      	         			ld<="ZZZZZZZZ";
	     	         		oe<=wr;
	     	         		we<=not wr;
      	         		else
	              			if(wr='1') 
	              			then
--	                     				if(ready='0') 
--	                     				then
--	                             				reg<=ld;
--	                     				else
--	                             				ld<="ZZZZZZZZ";
--	                     				end if;
	              			else
	                      			ld<=reg;
	              			end if;
	              		end if;
         		end if;
	end process;


 	process(regclk)
 	begin
       		if(regclk'event and regclk='1')
      	         	then      	         		
      	         		
      	         		int1<= not int;
      	         		int2<= not int1;
      	         		int3<= not int2;
      	         		int4<= not int3;
      	         		lint<=not int;
      	         		
      	           	end if;
      	           	
        	end process;
 	
      	           	
        	         	 	
      	process(onoffa,int4)
	begin
		if(onoffa'event and onoffa='1')
		then
			int<='1';
		end if;
		if(int='1' and int4='1')
		then
		  	int<='0';
		end if;
	end process;
end Behavioral;