a90541_timesim.vhd

采用9054做为板卡与计算机通信的媒介

      I1 => sa_4_OBUF_BUF0_D2,
      O => sa_4_OBUF_BUF0_D
    );
  sa_4_OBUF_BUF0_D1_207 : X_ZERO
    port map (
      O => sa_4_OBUF_BUF0_D1
    );
  sa_4_OBUF_BUF0_D2_208 : X_AND2
    port map (
      I0 => sa_4_OBUF,
      I1 => sa_4_OBUF,
      O => sa_4_OBUF_BUF0_D2
    );
  sa_5_OBUF_BUF0_209 : X_BUF
    port map (
      I => sa_5_OBUF_BUF0_Q,
      O => sa_5_OBUF_BUF0
    );
  sa_5_OBUF_BUF0_Q_210 : X_BUF
    port map (
      I => sa_5_OBUF_BUF0_D,
      O => sa_5_OBUF_BUF0_Q
    );
  sa_5_OBUF_BUF0_D_211 : X_XOR2
    port map (
      I0 => sa_5_OBUF_BUF0_D1,
      I1 => sa_5_OBUF_BUF0_D2,
      O => sa_5_OBUF_BUF0_D
    );
  sa_5_OBUF_BUF0_D1_212 : X_ZERO
    port map (
      O => sa_5_OBUF_BUF0_D1
    );
  sa_5_OBUF_BUF0_D2_213 : X_AND2
    port map (
      I0 => sa_5_OBUF,
      I1 => sa_5_OBUF,
      O => sa_5_OBUF_BUF0_D2
    );
  sa_6_OBUF_BUF0_214 : X_BUF
    port map (
      I => sa_6_OBUF_BUF0_Q,
      O => sa_6_OBUF_BUF0
    );
  sa_6_OBUF_BUF0_Q_215 : X_BUF
    port map (
      I => sa_6_OBUF_BUF0_D,
      O => sa_6_OBUF_BUF0_Q
    );
  sa_6_OBUF_BUF0_D_216 : X_XOR2
    port map (
      I0 => sa_6_OBUF_BUF0_D1,
      I1 => sa_6_OBUF_BUF0_D2,
      O => sa_6_OBUF_BUF0_D
    );
  sa_6_OBUF_BUF0_D1_217 : X_ZERO
    port map (
      O => sa_6_OBUF_BUF0_D1
    );
  sa_6_OBUF_BUF0_D2_218 : X_AND2
    port map (
      I0 => sa_6_OBUF,
      I1 => sa_6_OBUF,
      O => sa_6_OBUF_BUF0_D2
    );
  sa_7_OBUF_BUF0_219 : X_BUF
    port map (
      I => sa_7_OBUF_BUF0_Q,
      O => sa_7_OBUF_BUF0
    );
  sa_7_OBUF_BUF0_Q_220 : X_BUF
    port map (
      I => sa_7_OBUF_BUF0_D,
      O => sa_7_OBUF_BUF0_Q
    );
  sa_7_OBUF_BUF0_D_221 : X_XOR2
    port map (
      I0 => sa_7_OBUF_BUF0_D1,
      I1 => sa_7_OBUF_BUF0_D2,
      O => sa_7_OBUF_BUF0_D
    );
  sa_7_OBUF_BUF0_D1_222 : X_ZERO
    port map (
      O => sa_7_OBUF_BUF0_D1
    );
  sa_7_OBUF_BUF0_D2_223 : X_AND2
    port map (
      I0 => sa_7_OBUF,
      I1 => sa_7_OBUF,
      O => sa_7_OBUF_BUF0_D2
    );
  sa_8_OBUF_BUF0_224 : X_BUF
    port map (
      I => sa_8_OBUF_BUF0_Q,
      O => sa_8_OBUF_BUF0
    );
  sa_8_OBUF_BUF0_Q_225 : X_BUF
    port map (
      I => sa_8_OBUF_BUF0_D,
      O => sa_8_OBUF_BUF0_Q
    );
  sa_8_OBUF_BUF0_D_226 : X_XOR2
    port map (
      I0 => sa_8_OBUF_BUF0_D1,
      I1 => sa_8_OBUF_BUF0_D2,
      O => sa_8_OBUF_BUF0_D
    );
  sa_8_OBUF_BUF0_D1_227 : X_ZERO
    port map (
      O => sa_8_OBUF_BUF0_D1
    );
  sa_8_OBUF_BUF0_D2_228 : X_AND2
    port map (
      I0 => sa_8_OBUF,
      I1 => sa_8_OBUF,
      O => sa_8_OBUF_BUF0_D2
    );
  sa_9_OBUF_BUF0_229 : X_BUF
    port map (
      I => sa_9_OBUF_BUF0_Q,
      O => sa_9_OBUF_BUF0
    );
  sa_9_OBUF_BUF0_Q_230 : X_BUF
    port map (
      I => sa_9_OBUF_BUF0_D,
      O => sa_9_OBUF_BUF0_Q
    );
  sa_9_OBUF_BUF0_D_231 : X_XOR2
    port map (
      I0 => sa_9_OBUF_BUF0_D1,
      I1 => sa_9_OBUF_BUF0_D2,
      O => sa_9_OBUF_BUF0_D
    );
  sa_9_OBUF_BUF0_D1_232 : X_ZERO
    port map (
      O => sa_9_OBUF_BUF0_D1
    );
  sa_9_OBUF_BUF0_D2_233 : X_AND2
    port map (
      I0 => sa_9_OBUF,
      I1 => sa_9_OBUF,
      O => sa_9_OBUF_BUF0_D2
    );
  Mtridata_ld_7_Q_234 : X_BUF
    port map (
      I => Mtridata_ld_7_Q_2,
      O => Mtridata_ld_7_Q
    );
  Mtridata_ld_7_Q_235 : X_BUF
    port map (
      I => Mtridata_ld_7_D,
      O => Mtridata_ld_7_Q_2
    );
  Mtridata_ld_7_D_236 : X_XOR2
    port map (
      I0 => Mtridata_ld_7_D1,
      I1 => Mtridata_ld_7_D2,
      O => Mtridata_ld_7_D
    );
  Mtridata_ld_7_D1_237 : X_ZERO
    port map (
      O => Mtridata_ld_7_D1
    );
  Mtridata_ld_7_D2_238 : X_ZERO
    port map (
      O => Mtridata_ld_7_D2
    );
  Mtridata_ld_7_BUF0_239 : X_BUF
    port map (
      I => Mtridata_ld_7_BUF0_Q,
      O => Mtridata_ld_7_BUF0
    );
  Mtridata_ld_7_BUF0_Q_240 : X_BUF
    port map (
      I => Mtridata_ld_7_BUF0_D,
      O => Mtridata_ld_7_BUF0_Q
    );
  Mtridata_ld_7_BUF0_D_241 : X_XOR2
    port map (
      I0 => Mtridata_ld_7_BUF0_D1,
      I1 => Mtridata_ld_7_BUF0_D2,
      O => Mtridata_ld_7_BUF0_D
    );
  Mtridata_ld_7_BUF0_D1_242 : X_ZERO
    port map (
      O => Mtridata_ld_7_BUF0_D1
    );
  Mtridata_ld_7_BUF0_D2_243 : X_ZERO
    port map (
      O => Mtridata_ld_7_BUF0_D2
    );
  Mtridata_ld_7_BUF1_244 : X_BUF
    port map (
      I => Mtridata_ld_7_BUF1_Q,
      O => Mtridata_ld_7_BUF1
    );
  Mtridata_ld_7_BUF1_Q_245 : X_BUF
    port map (
      I => Mtridata_ld_7_BUF1_D,
      O => Mtridata_ld_7_BUF1_Q
    );
  Mtridata_ld_7_BUF1_D_246 : X_XOR2
    port map (
      I0 => Mtridata_ld_7_BUF1_D1,
      I1 => Mtridata_ld_7_BUF1_D2,
      O => Mtridata_ld_7_BUF1_D
    );
  Mtridata_ld_7_BUF1_D1_247 : X_ZERO
    port map (
      O => Mtridata_ld_7_BUF1_D1
    );
  Mtridata_ld_7_BUF1_D2_248 : X_ZERO
    port map (
      O => Mtridata_ld_7_BUF1_D2
    );
  Mtridata_ld_7_BUF2_249 : X_BUF
    port map (
      I => Mtridata_ld_7_BUF2_Q,
      O => Mtridata_ld_7_BUF2
    );
  Mtridata_ld_7_BUF2_Q_250 : X_BUF
    port map (
      I => Mtridata_ld_7_BUF2_D,
      O => Mtridata_ld_7_BUF2_Q
    );
  Mtridata_ld_7_BUF2_D_251 : X_XOR2
    port map (
      I0 => Mtridata_ld_7_BUF2_D1,
      I1 => Mtridata_ld_7_BUF2_D2,
      O => Mtridata_ld_7_BUF2_D
    );
  Mtridata_ld_7_BUF2_D1_252 : X_ZERO
    port map (
      O => Mtridata_ld_7_BUF2_D1
    );
  Mtridata_ld_7_BUF2_D2_253 : X_ZERO
    port map (
      O => Mtridata_ld_7_BUF2_D2
    );
  Mtridata_ld_7_BUF3_254 : X_BUF
    port map (
      I => Mtridata_ld_7_BUF3_Q,
      O => Mtridata_ld_7_BUF3
    );
  Mtridata_ld_7_BUF3_Q_255 : X_BUF
    port map (
      I => Mtridata_ld_7_BUF3_D,
      O => Mtridata_ld_7_BUF3_Q
    );
  Mtridata_ld_7_BUF3_D_256 : X_XOR2
    port map (
      I0 => Mtridata_ld_7_BUF3_D1,
      I1 => Mtridata_ld_7_BUF3_D2,
      O => Mtridata_ld_7_BUF3_D
    );
  Mtridata_ld_7_BUF3_D1_257 : X_ZERO
    port map (
      O => Mtridata_ld_7_BUF3_D1
    );
  Mtridata_ld_7_BUF3_D2_258 : X_ZERO
    port map (
      O => Mtridata_ld_7_BUF3_D2
    );
  Mtridata_ld_7_BUF4_259 : X_BUF
    port map (
      I => Mtridata_ld_7_BUF4_Q,
      O => Mtridata_ld_7_BUF4
    );
  Mtridata_ld_7_BUF4_Q_260 : X_BUF
    port map (
      I => Mtridata_ld_7_BUF4_D,
      O => Mtridata_ld_7_BUF4_Q
    );
  Mtridata_ld_7_BUF4_D_261 : X_XOR2
    port map (
      I0 => Mtridata_ld_7_BUF4_D1,
      I1 => Mtridata_ld_7_BUF4_D2,
      O => Mtridata_ld_7_BUF4_D
    );
  Mtridata_ld_7_BUF4_D1_262 : X_ZERO
    port map (
      O => Mtridata_ld_7_BUF4_D1
    );
  Mtridata_ld_7_BUF4_D2_263 : X_ZERO
    port map (
      O => Mtridata_ld_7_BUF4_D2
    );
  Mtridata_ld_7_BUF5_264 : X_BUF
    port map (
      I => Mtridata_ld_7_BUF5_Q,
      O => Mtridata_ld_7_BUF5
    );
  Mtridata_ld_7_BUF5_Q_265 : X_BUF
    port map (
      I => Mtridata_ld_7_BUF5_D,
      O => Mtridata_ld_7_BUF5_Q
    );
  Mtridata_ld_7_BUF5_D_266 : X_XOR2
    port map (
      I0 => Mtridata_ld_7_BUF5_D1,
      I1 => Mtridata_ld_7_BUF5_D2,
      O => Mtridata_ld_7_BUF5_D
    );
  Mtridata_ld_7_BUF5_D1_267 : X_ZERO
    port map (
      O => Mtridata_ld_7_BUF5_D1
    );
  Mtridata_ld_7_BUF5_D2_268 : X_ZERO
    port map (
      O => Mtridata_ld_7_BUF5_D2
    );
  Mtridata_ld_7_BUF6_269 : X_BUF
    port map (
      I => Mtridata_ld_7_BUF6_Q,
      O => Mtridata_ld_7_BUF6
    );
  Mtridata_ld_7_BUF6_Q_270 : X_BUF
    port map (
      I => Mtridata_ld_7_BUF6_D,
      O => Mtridata_ld_7_BUF6_Q
    );
  Mtridata_ld_7_BUF6_D_271 : X_XOR2
    port map (
      I0 => Mtridata_ld_7_BUF6_D1,
      I1 => Mtridata_ld_7_BUF6_D2,
      O => Mtridata_ld_7_BUF6_D
    );
  Mtridata_ld_7_BUF6_D1_272 : X_ZERO
    port map (
      O => Mtridata_ld_7_BUF6_D1
    );
  Mtridata_ld_7_BUF6_D2_273 : X_ZERO
    port map (
      O => Mtridata_ld_7_BUF6_D2
    );
  Mtridata_ld_7_BUF7_274 : X_BUF
    port map (
      I => Mtridata_ld_7_BUF7_Q,
      O => Mtridata_ld_7_BUF7
    );
  Mtridata_ld_7_BUF7_Q_275 : X_BUF
    port map (
      I => Mtridata_ld_7_BUF7_D,
      O => Mtridata_ld_7_BUF7_Q
    );
  Mtridata_ld_7_BUF7_D_276 : X_XOR2
    port map (
      I0 => Mtridata_ld_7_BUF7_D1,
      I1 => Mtridata_ld_7_BUF7_D2,
      O => Mtridata_ld_7_BUF7_D
    );
  Mtridata_ld_7_BUF7_D1_277 : X_ZERO
    port map (
      O => Mtridata_ld_7_BUF7_D1
    );
  Mtridata_ld_7_BUF7_D2_278 : X_ZERO
    port map (
      O => Mtridata_ld_7_BUF7_D2
    );
  led2_OBUF_Q_279 : X_BUF
    port map (
      I => led2_OBUF_Q_3,
      O => led2_OBUF_Q
    );
  led2_OBUF_Q_280 : X_BUF
    port map (
      I => led2_OBUF_D,
      O => led2_OBUF_Q_3
    );
  led2_OBUF_D_281 : X_XOR2
    port map (
      I0 => led2_OBUF_D1,
      I1 => led2_OBUF_D2,
      O => led2_OBUF_D
    );
  led2_OBUF_D1_282 : X_ZERO
    port map (
      O => led2_OBUF_D1
    );
  led2_OBUF_D2_283 : X_ONE
    port map (
      O => led2_OBUF_D2
    );
  NlwInverterBlock_Mtrien_ld_D2_PT_0_IN0 : X_INV
    port map (
      I => cpld_IBUF,
      O => NlwInverterSignal_Mtrien_ld_D2_PT_0_IN0
    );
  NlwInverterBlock_Mtrien_ld_D2_PT_0_IN1 : X_INV
    port map (
      I => cpld_IBUF,
      O => NlwInverterSignal_Mtrien_ld_D2_PT_0_IN1
    );
  NlwInverterBlock_Mtrien_ld_TRST_IN0 : X_INV
    port map (
      I => Mtrien_ld,
      O => NlwInverterSignal_Mtrien_ld_TRST_IN0
    );
  NlwInverterBlock_Mtrien_ld_TRST_IN1 : X_INV
    port map (
      I => Mtrien_ld,
      O => NlwInverterSignal_Mtrien_ld_TRST_IN1
    );
  NlwInverterBlock_oe_OBUF_CE_IN0 : X_INV
    port map (
      I => cpld_IBUF,
      O => NlwInverterSignal_oe_OBUF_CE_IN0
    );
  NlwInverterBlock_oe_OBUF_CE_IN1 : X_INV
    port map (
      I => cpld_IBUF,
      O => NlwInverterSignal_oe_OBUF_CE_IN1
    );
  NlwInverterBlock_ready_OBUF_D2_PT_0_IN0 : X_INV
    port map (
      I => blast_IBUF,
      O => NlwInverterSignal_ready_OBUF_D2_PT_0_IN0
    );
  NlwInverterBlock_ready_OBUF_D2_PT_0_IN1 : X_INV
    port map (
      I => blast_IBUF,
      O => NlwInverterSignal_ready_OBUF_D2_PT_0_IN1
    );
  NlwInverterBlock_we_OBUF_D2_IN0 : X_INV
    port map (
      I => wr_IBUF,
      O => NlwInverterSignal_we_OBUF_D2_IN0
    );
  NlwInverterBlock_we_OBUF_D2_IN1 : X_INV
    port map (
      I => wr_IBUF,
      O => NlwInverterSignal_we_OBUF_D2_IN1
    );
  NlwInverterBlock_we_OBUF_CE_IN0 : X_INV
    port map (
      I => cpld_IBUF,
      O => NlwInverterSignal_we_OBUF_CE_IN0
    );
  NlwInverterBlock_we_OBUF_CE_IN1 : X_INV
    port map (
      I => cpld_IBUF,
      O => NlwInverterSignal_we_OBUF_CE_IN1
    );
  NlwInverterBlock_lint_OBUF_D2_IN0 : X_INV
    port map (
      I => int,
      O => NlwInverterSignal_lint_OBUF_D2_IN0
    );
  NlwInverterBlock_lint_OBUF_D2_IN1 : X_INV
    port map (
      I => int,
      O => NlwInverterSignal_lint_OBUF_D2_IN1
    );
  NlwInverterBlock_int2_D2_IN0 : X_INV
    port map (
      I => lint_OBUF,
      O => NlwInverterSignal_int2_D2_IN0
    );
  NlwInverterBlock_int2_D2_IN1 : X_INV
    port map (
      I => lint_OBUF,
      O => NlwInverterSignal_int2_D2_IN1
    );
  NlwInverterBlock_int3_D2_IN0 : X_INV
    port map (
      I => int2,
      O => NlwInverterSignal_int3_D2_IN0
    );
  NlwInverterBlock_int3_D2_IN1 : X_INV
    port map (
      I => int2,
      O => NlwInverterSignal_int3_D2_IN1
    );
  NlwInverterBlock_int4_D2_IN0 : X_INV
    port map (
      I => int3,
      O => NlwInverterSignal_int4_D2_IN0
    );
  NlwInverterBlock_int4_D2_IN1 : X_INV
    port map (
      I => int3,
      O => NlwInverterSignal_int4_D2_IN1
    );
  NlwInverterBlock_Mtrien_ld_BUF0_TRST_IN0 : X_INV
    port map (
      I => Mtrien_ld,
      O => NlwInverterSignal_Mtrien_ld_BUF0_TRST_IN0
    );
  NlwInverterBlock_Mtrien_ld_BUF0_TRST_IN1 : X_INV
    port map (
      I => Mtrien_ld,
      O => NlwInverterSignal_Mtrien_ld_BUF0_TRST_IN1
    );
  NlwInverterBlock_Mtrien_ld_BUF1_TRST_IN0 : X_INV
    port map (
      I => Mtrien_ld,
      O => NlwInverterSignal_Mtrien_ld_BUF1_TRST_IN0
    );
  NlwInverterBlock_Mtrien_ld_BUF1_TRST_IN1 : X_INV
    port map (
      I => Mtrien_ld,
      O => NlwInverterSignal_Mtrien_ld_BUF1_TRST_IN1
    );
  NlwInverterBlock_Mtrien_ld_BUF2_TRST_IN0 : X_INV
    port map (
      I => Mtrien_ld,
      O => NlwInverterSignal_Mtrien_ld_BUF2_TRST_IN0
    );
  NlwInverterBlock_Mtrien_ld_BUF2_TRST_IN1 : X_INV
    port map (
      I => Mtrien_ld,
      O => NlwInverterSignal_Mtrien_ld_BUF2_TRST_IN1
    );
  NlwInverterBlock_Mtrien_ld_BUF3_TRST_IN0 : X_INV
    port map (
      I => Mtrien_ld,
      O => NlwInverterSignal_Mtrien_ld_BUF3_TRST_IN0
    );
  NlwInverterBlock_Mtrien_ld_BUF3_TRST_IN1 : X_INV
    port map (
      I => Mtrien_ld,
      O => NlwInverterSignal_Mtrien_ld_BUF3_TRST_IN1
    );
  NlwInverterBlock_Mtrien_ld_BUF4_TRST_IN0 : X_INV
    port map (
      I => Mtrien_ld,
      O => NlwInverterSignal_Mtrien_ld_BUF4_TRST_IN0
    );
  NlwInverterBlock_Mtrien_ld_BUF4_TRST_IN1 : X_INV
    port map (
      I => Mtrien_ld,
      O => NlwInverterSignal_Mtrien_ld_BUF4_TRST_IN1
    );
  NlwInverterBlock_Mtrien_ld_BUF5_TRST_IN0 : X_INV
    port map (
      I => Mtrien_ld,
      O => NlwInverterSignal_Mtrien_ld_BUF5_TRST_IN0
    );
  NlwInverterBlock_Mtrien_ld_BUF5_TRST_IN1 : X_INV
    port map (
      I => Mtrien_ld,
      O => NlwInverterSignal_Mtrien_ld_BUF5_TRST_IN1
    );
  NlwInverterBlock_Mtrien_ld_BUF6_TRST_IN0 : X_INV
    port map (
      I => Mtrien_ld,
      O => NlwInverterSignal_Mtrien_ld_BUF6_TRST_IN0
    );
  NlwInverterBlock_Mtrien_ld_BUF6_TRST_IN1 : X_INV
    port map (
      I => Mtrien_ld,
      O => NlwInverterSignal_Mtrien_ld_BUF6_TRST_IN1
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => PRLD);

end Structure;