a90541_timesim.vhd

采用9054做为板卡与计算机通信的媒介

  Mtrien_ld_BUF0_D2_99 : X_AND2
    port map (
      I0 => Mtrien_ld,
      I1 => Mtrien_ld,
      O => Mtrien_ld_BUF0_D2
    );
  Mtrien_ld_BUF0_TRST_100 : X_AND2
    port map (
      I0 => NlwInverterSignal_Mtrien_ld_BUF0_TRST_IN0,
      I1 => NlwInverterSignal_Mtrien_ld_BUF0_TRST_IN1,
      O => Mtrien_ld_BUF0_TRST
    );
  Mtrien_ld_BUF1_101 : X_BUF
    port map (
      I => Mtrien_ld_BUF1_Q,
      O => Mtrien_ld_BUF1
    );
  Mtrien_ld_BUF1_OE_102 : X_BUF
    port map (
      I => Mtrien_ld_BUF1_BUFOE_OUT,
      O => Mtrien_ld_BUF1_OE
    );
  Mtrien_ld_BUF1_BUFOE_OUT_103 : X_BUF
    port map (
      I => Mtrien_ld_BUF1_TRST,
      O => Mtrien_ld_BUF1_BUFOE_OUT
    );
  Mtrien_ld_BUF1_Q_104 : X_BUF
    port map (
      I => Mtrien_ld_BUF1_D,
      O => Mtrien_ld_BUF1_Q
    );
  Mtrien_ld_BUF1_D_105 : X_XOR2
    port map (
      I0 => Mtrien_ld_BUF1_D1,
      I1 => Mtrien_ld_BUF1_D2,
      O => Mtrien_ld_BUF1_D
    );
  Mtrien_ld_BUF1_D1_106 : X_ZERO
    port map (
      O => Mtrien_ld_BUF1_D1
    );
  Mtrien_ld_BUF1_D2_107 : X_AND2
    port map (
      I0 => Mtrien_ld,
      I1 => Mtrien_ld,
      O => Mtrien_ld_BUF1_D2
    );
  Mtrien_ld_BUF1_TRST_108 : X_AND2
    port map (
      I0 => NlwInverterSignal_Mtrien_ld_BUF1_TRST_IN0,
      I1 => NlwInverterSignal_Mtrien_ld_BUF1_TRST_IN1,
      O => Mtrien_ld_BUF1_TRST
    );
  Mtrien_ld_BUF2_109 : X_BUF
    port map (
      I => Mtrien_ld_BUF2_Q,
      O => Mtrien_ld_BUF2
    );
  Mtrien_ld_BUF2_OE_110 : X_BUF
    port map (
      I => Mtrien_ld_BUF2_BUFOE_OUT,
      O => Mtrien_ld_BUF2_OE
    );
  Mtrien_ld_BUF2_BUFOE_OUT_111 : X_BUF
    port map (
      I => Mtrien_ld_BUF2_TRST,
      O => Mtrien_ld_BUF2_BUFOE_OUT
    );
  Mtrien_ld_BUF2_Q_112 : X_BUF
    port map (
      I => Mtrien_ld_BUF2_D,
      O => Mtrien_ld_BUF2_Q
    );
  Mtrien_ld_BUF2_D_113 : X_XOR2
    port map (
      I0 => Mtrien_ld_BUF2_D1,
      I1 => Mtrien_ld_BUF2_D2,
      O => Mtrien_ld_BUF2_D
    );
  Mtrien_ld_BUF2_D1_114 : X_ZERO
    port map (
      O => Mtrien_ld_BUF2_D1
    );
  Mtrien_ld_BUF2_D2_115 : X_AND2
    port map (
      I0 => Mtrien_ld,
      I1 => Mtrien_ld,
      O => Mtrien_ld_BUF2_D2
    );
  Mtrien_ld_BUF2_TRST_116 : X_AND2
    port map (
      I0 => NlwInverterSignal_Mtrien_ld_BUF2_TRST_IN0,
      I1 => NlwInverterSignal_Mtrien_ld_BUF2_TRST_IN1,
      O => Mtrien_ld_BUF2_TRST
    );
  Mtrien_ld_BUF3_117 : X_BUF
    port map (
      I => Mtrien_ld_BUF3_Q,
      O => Mtrien_ld_BUF3
    );
  Mtrien_ld_BUF3_OE_118 : X_BUF
    port map (
      I => Mtrien_ld_BUF3_BUFOE_OUT,
      O => Mtrien_ld_BUF3_OE
    );
  Mtrien_ld_BUF3_BUFOE_OUT_119 : X_BUF
    port map (
      I => Mtrien_ld_BUF3_TRST,
      O => Mtrien_ld_BUF3_BUFOE_OUT
    );
  Mtrien_ld_BUF3_Q_120 : X_BUF
    port map (
      I => Mtrien_ld_BUF3_D,
      O => Mtrien_ld_BUF3_Q
    );
  Mtrien_ld_BUF3_D_121 : X_XOR2
    port map (
      I0 => Mtrien_ld_BUF3_D1,
      I1 => Mtrien_ld_BUF3_D2,
      O => Mtrien_ld_BUF3_D
    );
  Mtrien_ld_BUF3_D1_122 : X_ZERO
    port map (
      O => Mtrien_ld_BUF3_D1
    );
  Mtrien_ld_BUF3_D2_123 : X_AND2
    port map (
      I0 => Mtrien_ld,
      I1 => Mtrien_ld,
      O => Mtrien_ld_BUF3_D2
    );
  Mtrien_ld_BUF3_TRST_124 : X_AND2
    port map (
      I0 => NlwInverterSignal_Mtrien_ld_BUF3_TRST_IN0,
      I1 => NlwInverterSignal_Mtrien_ld_BUF3_TRST_IN1,
      O => Mtrien_ld_BUF3_TRST
    );
  Mtrien_ld_BUF4_125 : X_BUF
    port map (
      I => Mtrien_ld_BUF4_Q,
      O => Mtrien_ld_BUF4
    );
  Mtrien_ld_BUF4_OE_126 : X_BUF
    port map (
      I => Mtrien_ld_BUF4_BUFOE_OUT,
      O => Mtrien_ld_BUF4_OE
    );
  Mtrien_ld_BUF4_BUFOE_OUT_127 : X_BUF
    port map (
      I => Mtrien_ld_BUF4_TRST,
      O => Mtrien_ld_BUF4_BUFOE_OUT
    );
  Mtrien_ld_BUF4_Q_128 : X_BUF
    port map (
      I => Mtrien_ld_BUF4_D,
      O => Mtrien_ld_BUF4_Q
    );
  Mtrien_ld_BUF4_D_129 : X_XOR2
    port map (
      I0 => Mtrien_ld_BUF4_D1,
      I1 => Mtrien_ld_BUF4_D2,
      O => Mtrien_ld_BUF4_D
    );
  Mtrien_ld_BUF4_D1_130 : X_ZERO
    port map (
      O => Mtrien_ld_BUF4_D1
    );
  Mtrien_ld_BUF4_D2_131 : X_AND2
    port map (
      I0 => Mtrien_ld,
      I1 => Mtrien_ld,
      O => Mtrien_ld_BUF4_D2
    );
  Mtrien_ld_BUF4_TRST_132 : X_AND2
    port map (
      I0 => NlwInverterSignal_Mtrien_ld_BUF4_TRST_IN0,
      I1 => NlwInverterSignal_Mtrien_ld_BUF4_TRST_IN1,
      O => Mtrien_ld_BUF4_TRST
    );
  Mtrien_ld_BUF5_133 : X_BUF
    port map (
      I => Mtrien_ld_BUF5_Q,
      O => Mtrien_ld_BUF5
    );
  Mtrien_ld_BUF5_OE_134 : X_BUF
    port map (
      I => Mtrien_ld_BUF5_BUFOE_OUT,
      O => Mtrien_ld_BUF5_OE
    );
  Mtrien_ld_BUF5_BUFOE_OUT_135 : X_BUF
    port map (
      I => Mtrien_ld_BUF5_TRST,
      O => Mtrien_ld_BUF5_BUFOE_OUT
    );
  Mtrien_ld_BUF5_Q_136 : X_BUF
    port map (
      I => Mtrien_ld_BUF5_D,
      O => Mtrien_ld_BUF5_Q
    );
  Mtrien_ld_BUF5_D_137 : X_XOR2
    port map (
      I0 => Mtrien_ld_BUF5_D1,
      I1 => Mtrien_ld_BUF5_D2,
      O => Mtrien_ld_BUF5_D
    );
  Mtrien_ld_BUF5_D1_138 : X_ZERO
    port map (
      O => Mtrien_ld_BUF5_D1
    );
  Mtrien_ld_BUF5_D2_139 : X_AND2
    port map (
      I0 => Mtrien_ld,
      I1 => Mtrien_ld,
      O => Mtrien_ld_BUF5_D2
    );
  Mtrien_ld_BUF5_TRST_140 : X_AND2
    port map (
      I0 => NlwInverterSignal_Mtrien_ld_BUF5_TRST_IN0,
      I1 => NlwInverterSignal_Mtrien_ld_BUF5_TRST_IN1,
      O => Mtrien_ld_BUF5_TRST
    );
  Mtrien_ld_BUF6_141 : X_BUF
    port map (
      I => Mtrien_ld_BUF6_Q,
      O => Mtrien_ld_BUF6
    );
  Mtrien_ld_BUF6_OE_142 : X_BUF
    port map (
      I => Mtrien_ld_BUF6_BUFOE_OUT,
      O => Mtrien_ld_BUF6_OE
    );
  Mtrien_ld_BUF6_BUFOE_OUT_143 : X_BUF
    port map (
      I => Mtrien_ld_BUF6_TRST,
      O => Mtrien_ld_BUF6_BUFOE_OUT
    );
  Mtrien_ld_BUF6_Q_144 : X_BUF
    port map (
      I => Mtrien_ld_BUF6_D,
      O => Mtrien_ld_BUF6_Q
    );
  Mtrien_ld_BUF6_D_145 : X_XOR2
    port map (
      I0 => Mtrien_ld_BUF6_D1,
      I1 => Mtrien_ld_BUF6_D2,
      O => Mtrien_ld_BUF6_D
    );
  Mtrien_ld_BUF6_D1_146 : X_ZERO
    port map (
      O => Mtrien_ld_BUF6_D1
    );
  Mtrien_ld_BUF6_D2_147 : X_AND2
    port map (
      I0 => Mtrien_ld,
      I1 => Mtrien_ld,
      O => Mtrien_ld_BUF6_D2
    );
  Mtrien_ld_BUF6_TRST_148 : X_AND2
    port map (
      I0 => NlwInverterSignal_Mtrien_ld_BUF6_TRST_IN0,
      I1 => NlwInverterSignal_Mtrien_ld_BUF6_TRST_IN1,
      O => Mtrien_ld_BUF6_TRST
    );
  lclk_OBUF_BUF0_149 : X_BUF
    port map (
      I => lclk_OBUF_BUF0_Q,
      O => lclk_OBUF_BUF0
    );
  lclk_OBUF_BUF0_Q_150 : X_BUF
    port map (
      I => lclk_OBUF_BUF0_D,
      O => lclk_OBUF_BUF0_Q
    );
  lclk_OBUF_BUF0_D_151 : X_XOR2
    port map (
      I0 => lclk_OBUF_BUF0_D1,
      I1 => lclk_OBUF_BUF0_D2,
      O => lclk_OBUF_BUF0_D
    );
  lclk_OBUF_BUF0_D1_152 : X_ZERO
    port map (
      O => lclk_OBUF_BUF0_D1
    );
  lclk_OBUF_BUF0_D2_153 : X_AND2
    port map (
      I0 => lclk_OBUF,
      I1 => lclk_OBUF,
      O => lclk_OBUF_BUF0_D2
    );
  led1_OBUF_BUF0_154 : X_BUF
    port map (
      I => led1_OBUF_BUF0_Q,
      O => led1_OBUF_BUF0
    );
  led1_OBUF_BUF0_Q_155 : X_BUF
    port map (
      I => led1_OBUF_BUF0_D,
      O => led1_OBUF_BUF0_Q
    );
  led1_OBUF_BUF0_D_156 : X_XOR2
    port map (
      I0 => led1_OBUF_BUF0_D1,
      I1 => led1_OBUF_BUF0_D2,
      O => led1_OBUF_BUF0_D
    );
  led1_OBUF_BUF0_D1_157 : X_ZERO
    port map (
      O => led1_OBUF_BUF0_D1
    );
  led1_OBUF_BUF0_D2_158 : X_AND2
    port map (
      I0 => led1_OBUF,
      I1 => led1_OBUF,
      O => led1_OBUF_BUF0_D2
    );
  sa_0_OBUF_BUF0_159 : X_BUF
    port map (
      I => sa_0_OBUF_BUF0_Q,
      O => sa_0_OBUF_BUF0
    );
  sa_0_OBUF_BUF0_Q_160 : X_BUF
    port map (
      I => sa_0_OBUF_BUF0_D,
      O => sa_0_OBUF_BUF0_Q
    );
  sa_0_OBUF_BUF0_D_161 : X_XOR2
    port map (
      I0 => sa_0_OBUF_BUF0_D1,
      I1 => sa_0_OBUF_BUF0_D2,
      O => sa_0_OBUF_BUF0_D
    );
  sa_0_OBUF_BUF0_D1_162 : X_ZERO
    port map (
      O => sa_0_OBUF_BUF0_D1
    );
  sa_0_OBUF_BUF0_D2_163 : X_AND2
    port map (
      I0 => sa_0_OBUF,
      I1 => sa_0_OBUF,
      O => sa_0_OBUF_BUF0_D2
    );
  sa_10_OBUF_BUF0_164 : X_BUF
    port map (
      I => sa_10_OBUF_BUF0_Q,
      O => sa_10_OBUF_BUF0
    );
  sa_10_OBUF_BUF0_Q_165 : X_BUF
    port map (
      I => sa_10_OBUF_BUF0_D,
      O => sa_10_OBUF_BUF0_Q
    );
  sa_10_OBUF_BUF0_D_166 : X_XOR2
    port map (
      I0 => sa_10_OBUF_BUF0_D1,
      I1 => sa_10_OBUF_BUF0_D2,
      O => sa_10_OBUF_BUF0_D
    );
  sa_10_OBUF_BUF0_D1_167 : X_ZERO
    port map (
      O => sa_10_OBUF_BUF0_D1
    );
  sa_10_OBUF_BUF0_D2_168 : X_AND2
    port map (
      I0 => sa_10_OBUF,
      I1 => sa_10_OBUF,
      O => sa_10_OBUF_BUF0_D2
    );
  sa_11_OBUF_BUF0_169 : X_BUF
    port map (
      I => sa_11_OBUF_BUF0_Q,
      O => sa_11_OBUF_BUF0
    );
  sa_11_OBUF_BUF0_Q_170 : X_BUF
    port map (
      I => sa_11_OBUF_BUF0_D,
      O => sa_11_OBUF_BUF0_Q
    );
  sa_11_OBUF_BUF0_D_171 : X_XOR2
    port map (
      I0 => sa_11_OBUF_BUF0_D1,
      I1 => sa_11_OBUF_BUF0_D2,
      O => sa_11_OBUF_BUF0_D
    );
  sa_11_OBUF_BUF0_D1_172 : X_ZERO
    port map (
      O => sa_11_OBUF_BUF0_D1
    );
  sa_11_OBUF_BUF0_D2_173 : X_AND2
    port map (
      I0 => sa_11_OBUF,
      I1 => sa_11_OBUF,
      O => sa_11_OBUF_BUF0_D2
    );
  sa_12_OBUF_BUF0_174 : X_BUF
    port map (
      I => sa_12_OBUF_BUF0_Q,
      O => sa_12_OBUF_BUF0
    );
  sa_12_OBUF_BUF0_Q_175 : X_BUF
    port map (
      I => sa_12_OBUF_BUF0_D,
      O => sa_12_OBUF_BUF0_Q
    );
  sa_12_OBUF_BUF0_D_176 : X_XOR2
    port map (
      I0 => sa_12_OBUF_BUF0_D1,
      I1 => sa_12_OBUF_BUF0_D2,
      O => sa_12_OBUF_BUF0_D
    );
  sa_12_OBUF_BUF0_D1_177 : X_ZERO
    port map (
      O => sa_12_OBUF_BUF0_D1
    );
  sa_12_OBUF_BUF0_D2_178 : X_AND2
    port map (
      I0 => sa_12_OBUF,
      I1 => sa_12_OBUF,
      O => sa_12_OBUF_BUF0_D2
    );
  sa_13_OBUF_BUF0_179 : X_BUF
    port map (
      I => sa_13_OBUF_BUF0_Q,
      O => sa_13_OBUF_BUF0
    );
  sa_13_OBUF_BUF0_Q_180 : X_BUF
    port map (
      I => sa_13_OBUF_BUF0_D,
      O => sa_13_OBUF_BUF0_Q
    );
  sa_13_OBUF_BUF0_D_181 : X_XOR2
    port map (
      I0 => sa_13_OBUF_BUF0_D1,
      I1 => sa_13_OBUF_BUF0_D2,
      O => sa_13_OBUF_BUF0_D
    );
  sa_13_OBUF_BUF0_D1_182 : X_ZERO
    port map (
      O => sa_13_OBUF_BUF0_D1
    );
  sa_13_OBUF_BUF0_D2_183 : X_AND2
    port map (
      I0 => sa_13_OBUF,
      I1 => sa_13_OBUF,
      O => sa_13_OBUF_BUF0_D2
    );
  sa_14_OBUF_BUF0_184 : X_BUF
    port map (
      I => sa_14_OBUF_BUF0_Q,
      O => sa_14_OBUF_BUF0
    );
  sa_14_OBUF_BUF0_Q_185 : X_BUF
    port map (
      I => sa_14_OBUF_BUF0_D,
      O => sa_14_OBUF_BUF0_Q
    );
  sa_14_OBUF_BUF0_D_186 : X_XOR2
    port map (
      I0 => sa_14_OBUF_BUF0_D1,
      I1 => sa_14_OBUF_BUF0_D2,
      O => sa_14_OBUF_BUF0_D
    );
  sa_14_OBUF_BUF0_D1_187 : X_ZERO
    port map (
      O => sa_14_OBUF_BUF0_D1
    );
  sa_14_OBUF_BUF0_D2_188 : X_AND2
    port map (
      I0 => sa_14_OBUF,
      I1 => sa_14_OBUF,
      O => sa_14_OBUF_BUF0_D2
    );
  sa_1_OBUF_BUF0_189 : X_BUF
    port map (
      I => sa_1_OBUF_BUF0_Q,
      O => sa_1_OBUF_BUF0
    );
  sa_1_OBUF_BUF0_Q_190 : X_BUF
    port map (
      I => sa_1_OBUF_BUF0_D,
      O => sa_1_OBUF_BUF0_Q
    );
  sa_1_OBUF_BUF0_D_191 : X_XOR2
    port map (
      I0 => sa_1_OBUF_BUF0_D1,
      I1 => sa_1_OBUF_BUF0_D2,
      O => sa_1_OBUF_BUF0_D
    );
  sa_1_OBUF_BUF0_D1_192 : X_ZERO
    port map (
      O => sa_1_OBUF_BUF0_D1
    );
  sa_1_OBUF_BUF0_D2_193 : X_AND2
    port map (
      I0 => sa_1_OBUF,
      I1 => sa_1_OBUF,
      O => sa_1_OBUF_BUF0_D2
    );
  sa_2_OBUF_BUF0_194 : X_BUF
    port map (
      I => sa_2_OBUF_BUF0_Q,
      O => sa_2_OBUF_BUF0
    );
  sa_2_OBUF_BUF0_Q_195 : X_BUF
    port map (
      I => sa_2_OBUF_BUF0_D,
      O => sa_2_OBUF_BUF0_Q
    );
  sa_2_OBUF_BUF0_D_196 : X_XOR2
    port map (
      I0 => sa_2_OBUF_BUF0_D1,
      I1 => sa_2_OBUF_BUF0_D2,
      O => sa_2_OBUF_BUF0_D
    );
  sa_2_OBUF_BUF0_D1_197 : X_ZERO
    port map (
      O => sa_2_OBUF_BUF0_D1
    );
  sa_2_OBUF_BUF0_D2_198 : X_AND2
    port map (
      I0 => sa_2_OBUF,
      I1 => sa_2_OBUF,
      O => sa_2_OBUF_BUF0_D2
    );
  sa_3_OBUF_BUF0_199 : X_BUF
    port map (
      I => sa_3_OBUF_BUF0_Q,
      O => sa_3_OBUF_BUF0
    );
  sa_3_OBUF_BUF0_Q_200 : X_BUF
    port map (
      I => sa_3_OBUF_BUF0_D,
      O => sa_3_OBUF_BUF0_Q
    );
  sa_3_OBUF_BUF0_D_201 : X_XOR2
    port map (
      I0 => sa_3_OBUF_BUF0_D1,
      I1 => sa_3_OBUF_BUF0_D2,
      O => sa_3_OBUF_BUF0_D
    );
  sa_3_OBUF_BUF0_D1_202 : X_ZERO
    port map (
      O => sa_3_OBUF_BUF0_D1
    );
  sa_3_OBUF_BUF0_D2_203 : X_AND2
    port map (
      I0 => sa_3_OBUF,
      I1 => sa_3_OBUF,
      O => sa_3_OBUF_BUF0_D2
    );
  sa_4_OBUF_BUF0_204 : X_BUF
    port map (
      I => sa_4_OBUF_BUF0_Q,
      O => sa_4_OBUF_BUF0
    );
  sa_4_OBUF_BUF0_Q_205 : X_BUF
    port map (
      I => sa_4_OBUF_BUF0_D,
      O => sa_4_OBUF_BUF0_Q
    );
  sa_4_OBUF_BUF0_D_206 : X_XOR2
    port map (
      I0 => sa_4_OBUF_BUF0_D1,