a90541_timesim.vhd

采用9054做为板卡与计算机通信的媒介

    );
  ld_1_Q : X_TRI
    port map (
      I => Mtrien_ld_BUF5,
      CTL => Mtrien_ld_BUF5_OE,
      O => ld(1)
    );
  ld_0_Q : X_TRI
    port map (
      I => Mtrien_ld_BUF6,
      CTL => Mtrien_ld_BUF6_OE,
      O => ld(0)
    );
  lclk_33 : X_BUF
    port map (
      I => lclk_OBUF_BUF0,
      O => lclk
    );
  led1_34 : X_BUF
    port map (
      I => led1_OBUF_BUF0,
      O => led1
    );
  sa_0_Q : X_BUF
    port map (
      I => sa_0_OBUF_BUF0,
      O => sa(0)
    );
  sa_10_Q : X_BUF
    port map (
      I => sa_10_OBUF_BUF0,
      O => sa(10)
    );
  sa_11_Q : X_BUF
    port map (
      I => sa_11_OBUF_BUF0,
      O => sa(11)
    );
  sa_12_Q : X_BUF
    port map (
      I => sa_12_OBUF_BUF0,
      O => sa(12)
    );
  sa_13_Q : X_BUF
    port map (
      I => sa_13_OBUF_BUF0,
      O => sa(13)
    );
  sa_14_Q : X_BUF
    port map (
      I => sa_14_OBUF_BUF0,
      O => sa(14)
    );
  sa_1_Q : X_BUF
    port map (
      I => sa_1_OBUF_BUF0,
      O => sa(1)
    );
  sa_2_Q : X_BUF
    port map (
      I => sa_2_OBUF_BUF0,
      O => sa(2)
    );
  sa_3_Q : X_BUF
    port map (
      I => sa_3_OBUF_BUF0,
      O => sa(3)
    );
  sa_4_Q : X_BUF
    port map (
      I => sa_4_OBUF_BUF0,
      O => sa(4)
    );
  sa_5_Q : X_BUF
    port map (
      I => sa_5_OBUF_BUF0,
      O => sa(5)
    );
  sa_6_Q : X_BUF
    port map (
      I => sa_6_OBUF_BUF0,
      O => sa(6)
    );
  sa_7_Q : X_BUF
    port map (
      I => sa_7_OBUF_BUF0,
      O => sa(7)
    );
  sa_8_Q : X_BUF
    port map (
      I => sa_8_OBUF_BUF0,
      O => sa(8)
    );
  sa_9_Q : X_BUF
    port map (
      I => sa_9_OBUF_BUF0,
      O => sa(9)
    );
  led_7_Q : X_BUF
    port map (
      I => Mtridata_ld_7_Q,
      O => led(7)
    );
  led_6_Q : X_BUF
    port map (
      I => Mtridata_ld_7_BUF0,
      O => led(6)
    );
  led_5_Q : X_BUF
    port map (
      I => Mtridata_ld_7_BUF1,
      O => led(5)
    );
  led_4_Q : X_BUF
    port map (
      I => Mtridata_ld_7_BUF2,
      O => led(4)
    );
  led_3_Q : X_BUF
    port map (
      I => Mtridata_ld_7_BUF3,
      O => led(3)
    );
  led_2_Q : X_BUF
    port map (
      I => Mtridata_ld_7_BUF4,
      O => led(2)
    );
  led_1_Q : X_BUF
    port map (
      I => Mtridata_ld_7_BUF5,
      O => led(1)
    );
  led_0_Q : X_BUF
    port map (
      I => Mtridata_ld_7_BUF6,
      O => led(0)
    );
  ce_35 : X_BUF
    port map (
      I => Mtridata_ld_7_BUF7,
      O => ce
    );
  led2_36 : X_BUF
    port map (
      I => led2_OBUF_Q,
      O => led2
    );
  Mtrien_ld_Q_37 : X_BUF
    port map (
      I => Mtrien_ld_Q_0,
      O => Mtrien_ld_Q
    );
  Mtrien_ld_38 : X_BUF
    port map (
      I => Mtrien_ld_Q_0,
      O => Mtrien_ld
    );
  Mtrien_ld_OE_39 : X_BUF
    port map (
      I => Mtrien_ld_BUFOE_OUT,
      O => Mtrien_ld_OE
    );
  Mtrien_ld_BUFOE_OUT_40 : X_BUF
    port map (
      I => Mtrien_ld_TRST,
      O => Mtrien_ld_BUFOE_OUT
    );
  Mtrien_ld_REG : X_FF
    port map (
      I => Mtrien_ld_D,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => Gnd,
      RST => PRLD,
      O => Mtrien_ld_Q_0
    );
  Gnd_41 : X_ZERO
    port map (
      O => Gnd
    );
  Vcc_42 : X_ONE
    port map (
      O => Vcc
    );
  Mtrien_ld_D_43 : X_XOR2
    port map (
      I0 => Mtrien_ld_D1,
      I1 => Mtrien_ld_D2,
      O => Mtrien_ld_D
    );
  Mtrien_ld_D1_44 : X_ZERO
    port map (
      O => Mtrien_ld_D1
    );
  Mtrien_ld_D2_PT_0_45 : X_AND2
    port map (
      I0 => NlwInverterSignal_Mtrien_ld_D2_PT_0_IN0,
      I1 => NlwInverterSignal_Mtrien_ld_D2_PT_0_IN1,
      O => Mtrien_ld_D2_PT_0
    );
  Mtrien_ld_D2_PT_1_46 : X_AND2
    port map (
      I0 => wr_IBUF,
      I1 => Mtrien_ld,
      O => Mtrien_ld_D2_PT_1
    );
  Mtrien_ld_D2_47 : X_OR2
    port map (
      I0 => Mtrien_ld_D2_PT_0,
      I1 => Mtrien_ld_D2_PT_1,
      O => Mtrien_ld_D2
    );
  Mtrien_ld_TRST_48 : X_AND2
    port map (
      I0 => NlwInverterSignal_Mtrien_ld_TRST_IN0,
      I1 => NlwInverterSignal_Mtrien_ld_TRST_IN1,
      O => Mtrien_ld_TRST
    );
  oe_OBUF_49 : X_BUF
    port map (
      I => oe_OBUF_Q,
      O => oe_OBUF
    );
  oe_OBUF_REG : X_FF
    port map (
      I => oe_OBUF_D,
      CE => oe_OBUF_CE,
      CLK => FCLKIO_0,
      SET => Gnd,
      RST => PRLD,
      O => oe_OBUF_Q
    );
  oe_OBUF_D_50 : X_XOR2
    port map (
      I0 => oe_OBUF_D1,
      I1 => oe_OBUF_D2,
      O => oe_OBUF_D
    );
  oe_OBUF_D1_51 : X_ZERO
    port map (
      O => oe_OBUF_D1
    );
  oe_OBUF_D2_52 : X_AND2
    port map (
      I0 => wr_IBUF,
      I1 => wr_IBUF,
      O => oe_OBUF_D2
    );
  oe_OBUF_CE_53 : X_AND2
    port map (
      I0 => NlwInverterSignal_oe_OBUF_CE_IN0,
      I1 => NlwInverterSignal_oe_OBUF_CE_IN1,
      O => oe_OBUF_CE
    );
  ready_OBUF_54 : X_BUF
    port map (
      I => ready_OBUF_Q,
      O => ready_OBUF
    );
  ready_OBUF_UIM_55 : X_BUF
    port map (
      I => ready_OBUF_Q,
      O => ready_OBUF_UIM
    );
  ready_OBUF_REG : X_FF
    port map (
      I => ready_OBUF_D,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => PRLD,
      RST => Gnd,
      O => ready_OBUF_Q
    );
  ready_OBUF_D_56 : X_XOR2
    port map (
      I0 => ready_OBUF_D1,
      I1 => ready_OBUF_D2,
      O => ready_OBUF_D
    );
  ready_OBUF_D1_57 : X_ZERO
    port map (
      O => ready_OBUF_D1
    );
  ready_OBUF_D2_PT_0_58 : X_AND2
    port map (
      I0 => NlwInverterSignal_ready_OBUF_D2_PT_0_IN0,
      I1 => NlwInverterSignal_ready_OBUF_D2_PT_0_IN1,
      O => ready_OBUF_D2_PT_0
    );
  ready_OBUF_D2_PT_1_59 : X_AND2
    port map (
      I0 => ads_IBUF,
      I1 => ready_OBUF_UIM,
      O => ready_OBUF_D2_PT_1
    );
  ready_OBUF_D2_60 : X_OR2
    port map (
      I0 => ready_OBUF_D2_PT_0,
      I1 => ready_OBUF_D2_PT_1,
      O => ready_OBUF_D2
    );
  we_OBUF_61 : X_BUF
    port map (
      I => we_OBUF_Q,
      O => we_OBUF
    );
  we_OBUF_REG : X_FF
    port map (
      I => we_OBUF_D,
      CE => we_OBUF_CE,
      CLK => FCLKIO_0,
      SET => Gnd,
      RST => PRLD,
      O => we_OBUF_Q
    );
  we_OBUF_D_62 : X_XOR2
    port map (
      I0 => we_OBUF_D1,
      I1 => we_OBUF_D2,
      O => we_OBUF_D
    );
  we_OBUF_D1_63 : X_ZERO
    port map (
      O => we_OBUF_D1
    );
  we_OBUF_D2_64 : X_AND2
    port map (
      I0 => NlwInverterSignal_we_OBUF_D2_IN0,
      I1 => NlwInverterSignal_we_OBUF_D2_IN1,
      O => we_OBUF_D2
    );
  we_OBUF_CE_65 : X_AND2
    port map (
      I0 => NlwInverterSignal_we_OBUF_CE_IN0,
      I1 => NlwInverterSignal_we_OBUF_CE_IN1,
      O => we_OBUF_CE
    );
  lint_OBUF_Q_66 : X_BUF
    port map (
      I => lint_OBUF_Q_1,
      O => lint_OBUF_Q
    );
  lint_OBUF_67 : X_BUF
    port map (
      I => lint_OBUF_Q_1,
      O => lint_OBUF
    );
  lint_OBUF_REG : X_FF
    port map (
      I => lint_OBUF_D,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => Gnd,
      RST => PRLD,
      O => lint_OBUF_Q_1
    );
  lint_OBUF_D_68 : X_XOR2
    port map (
      I0 => lint_OBUF_D1,
      I1 => lint_OBUF_D2,
      O => lint_OBUF_D
    );
  lint_OBUF_D1_69 : X_ZERO
    port map (
      O => lint_OBUF_D1
    );
  lint_OBUF_D2_70 : X_AND2
    port map (
      I0 => NlwInverterSignal_lint_OBUF_D2_IN0,
      I1 => NlwInverterSignal_lint_OBUF_D2_IN1,
      O => lint_OBUF_D2
    );
  int_71 : X_BUF
    port map (
      I => int_Q,
      O => int
    );
  int_tsimcreated_prld_Q_72 : X_OR2
    port map (
      I0 => int_RSTF,
      I1 => PRLD,
      O => int_tsimcreated_prld_Q
    );
  int_REG : X_FF
    port map (
      I => int_D,
      CE => Vcc,
      CLK => FCLKIO_1,
      SET => Gnd,
      RST => int_tsimcreated_prld_Q,
      O => int_Q
    );
  int_D_73 : X_XOR2
    port map (
      I0 => int_D1,
      I1 => int_D2,
      O => int_D
    );
  int_D1_74 : X_ZERO
    port map (
      O => int_D1
    );
  int_D2_75 : X_ONE
    port map (
      O => int_D2
    );
  int_RSTF_76 : X_AND2
    port map (
      I0 => int,
      I1 => int4,
      O => int_RSTF
    );
  int2_77 : X_BUF
    port map (
      I => int2_Q,
      O => int2
    );
  int2_REG : X_FF
    port map (
      I => int2_D,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => Gnd,
      RST => PRLD,
      O => int2_Q
    );
  int2_D_78 : X_XOR2
    port map (
      I0 => int2_D1,
      I1 => int2_D2,
      O => int2_D
    );
  int2_D1_79 : X_ZERO
    port map (
      O => int2_D1
    );
  int2_D2_80 : X_AND2
    port map (
      I0 => NlwInverterSignal_int2_D2_IN0,
      I1 => NlwInverterSignal_int2_D2_IN1,
      O => int2_D2
    );
  int3_81 : X_BUF
    port map (
      I => int3_Q,
      O => int3
    );
  int3_REG : X_FF
    port map (
      I => int3_D,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => Gnd,
      RST => PRLD,
      O => int3_Q
    );
  int3_D_82 : X_XOR2
    port map (
      I0 => int3_D1,
      I1 => int3_D2,
      O => int3_D
    );
  int3_D1_83 : X_ZERO
    port map (
      O => int3_D1
    );
  int3_D2_84 : X_AND2
    port map (
      I0 => NlwInverterSignal_int3_D2_IN0,
      I1 => NlwInverterSignal_int3_D2_IN1,
      O => int3_D2
    );
  int4_85 : X_BUF
    port map (
      I => int4_Q,
      O => int4
    );
  int4_REG : X_FF
    port map (
      I => int4_D,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => Gnd,
      RST => PRLD,
      O => int4_Q
    );
  int4_D_86 : X_XOR2
    port map (
      I0 => int4_D1,
      I1 => int4_D2,
      O => int4_D
    );
  int4_D1_87 : X_ZERO
    port map (
      O => int4_D1
    );
  int4_D2_88 : X_AND2
    port map (
      I0 => NlwInverterSignal_int4_D2_IN0,
      I1 => NlwInverterSignal_int4_D2_IN1,
      O => int4_D2
    );
  lholda_OBUF_89 : X_BUF
    port map (
      I => lholda_OBUF_Q,
      O => lholda_OBUF
    );
  lholda_OBUF_REG : X_FF
    port map (
      I => lholda_OBUF_D,
      CE => Vcc,
      CLK => FCLKIO_0,
      SET => Gnd,
      RST => PRLD,
      O => lholda_OBUF_Q
    );
  lholda_OBUF_D_90 : X_XOR2
    port map (
      I0 => lholda_OBUF_D1,
      I1 => lholda_OBUF_D2,
      O => lholda_OBUF_D
    );
  lholda_OBUF_D1_91 : X_ZERO
    port map (
      O => lholda_OBUF_D1
    );
  lholda_OBUF_D2_92 : X_AND2
    port map (
      I0 => lhold_IBUF,
      I1 => lhold_IBUF,
      O => lholda_OBUF_D2
    );
  Mtrien_ld_BUF0_93 : X_BUF
    port map (
      I => Mtrien_ld_BUF0_Q,
      O => Mtrien_ld_BUF0
    );
  Mtrien_ld_BUF0_OE_94 : X_BUF
    port map (
      I => Mtrien_ld_BUF0_BUFOE_OUT,
      O => Mtrien_ld_BUF0_OE
    );
  Mtrien_ld_BUF0_BUFOE_OUT_95 : X_BUF
    port map (
      I => Mtrien_ld_BUF0_TRST,
      O => Mtrien_ld_BUF0_BUFOE_OUT
    );
  Mtrien_ld_BUF0_Q_96 : X_BUF
    port map (
      I => Mtrien_ld_BUF0_D,
      O => Mtrien_ld_BUF0_Q
    );
  Mtrien_ld_BUF0_D_97 : X_XOR2
    port map (
      I0 => Mtrien_ld_BUF0_D1,
      I1 => Mtrien_ld_BUF0_D2,
      O => Mtrien_ld_BUF0_D
    );
  Mtrien_ld_BUF0_D1_98 : X_ZERO
    port map (
      O => Mtrien_ld_BUF0_D1
    );