a90541_timesim.vhd

采用9054做为板卡与计算机通信的媒介

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: H.42
--  \   \         Application: netgen
--  /   /         Filename: a90541_timesim.vhd
-- /___/   /\     Timestamp: Thu Mar 15 20:09:58 2007
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim a90541.nga a90541_timesim.vhd 
-- Device	: XC95288XL-10-TQ144 (Speed File: Version 3.0)
-- Input file	: a90541.nga
-- Output file	: a90541_timesim.vhd
-- # of Entities	: 1
-- Design Name	: a90541.nga
-- Xilinx	: D:/tools/ISE7.1
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Verification Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity a90541 is
  port (
    main_clk : in STD_LOGIC := 'X'; 
    cpld : in STD_LOGIC := 'X'; 
    wr : in STD_LOGIC := 'X'; 
    blast : in STD_LOGIC := 'X'; 
    ads : in STD_LOGIC := 'X'; 
    onoffa : in STD_LOGIC := 'X'; 
    lhold : in STD_LOGIC := 'X'; 
    oe : out STD_LOGIC; 
    ready : out STD_LOGIC; 
    we : out STD_LOGIC; 
    lint : out STD_LOGIC; 
    lholda : out STD_LOGIC; 
    lclk : out STD_LOGIC; 
    led1 : out STD_LOGIC; 
    ce : out STD_LOGIC; 
    led2 : out STD_LOGIC; 
    la : in STD_LOGIC_VECTOR ( 14 downto 0 ); 
    ld : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    sa : out STD_LOGIC_VECTOR ( 14 downto 0 ); 
    led : out STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end a90541;

architecture Structure of a90541 is
  signal lclk_OBUF : STD_LOGIC; 
  signal FCLKIO_0 : STD_LOGIC; 
  signal cpld_IBUF : STD_LOGIC; 
  signal wr_IBUF : STD_LOGIC; 
  signal blast_IBUF : STD_LOGIC; 
  signal ads_IBUF : STD_LOGIC; 
  signal led1_OBUF : STD_LOGIC; 
  signal FCLKIO_1 : STD_LOGIC; 
  signal lhold_IBUF : STD_LOGIC; 
  signal sa_0_OBUF : STD_LOGIC; 
  signal sa_10_OBUF : STD_LOGIC; 
  signal sa_11_OBUF : STD_LOGIC; 
  signal sa_12_OBUF : STD_LOGIC; 
  signal sa_13_OBUF : STD_LOGIC; 
  signal sa_14_OBUF : STD_LOGIC; 
  signal sa_1_OBUF : STD_LOGIC; 
  signal sa_2_OBUF : STD_LOGIC; 
  signal sa_3_OBUF : STD_LOGIC; 
  signal sa_4_OBUF : STD_LOGIC; 
  signal sa_5_OBUF : STD_LOGIC; 
  signal sa_6_OBUF : STD_LOGIC; 
  signal sa_7_OBUF : STD_LOGIC; 
  signal sa_8_OBUF : STD_LOGIC; 
  signal sa_9_OBUF : STD_LOGIC; 
  signal Mtrien_ld_Q : STD_LOGIC; 
  signal Mtrien_ld_OE : STD_LOGIC; 
  signal oe_OBUF : STD_LOGIC; 
  signal ready_OBUF : STD_LOGIC; 
  signal we_OBUF : STD_LOGIC; 
  signal lint_OBUF_Q : STD_LOGIC; 
  signal lholda_OBUF : STD_LOGIC; 
  signal Mtrien_ld_BUF0 : STD_LOGIC; 
  signal Mtrien_ld_BUF0_OE : STD_LOGIC; 
  signal Mtrien_ld_BUF1 : STD_LOGIC; 
  signal Mtrien_ld_BUF1_OE : STD_LOGIC; 
  signal Mtrien_ld_BUF2 : STD_LOGIC; 
  signal Mtrien_ld_BUF2_OE : STD_LOGIC; 
  signal Mtrien_ld_BUF3 : STD_LOGIC; 
  signal Mtrien_ld_BUF3_OE : STD_LOGIC; 
  signal Mtrien_ld_BUF4 : STD_LOGIC; 
  signal Mtrien_ld_BUF4_OE : STD_LOGIC; 
  signal Mtrien_ld_BUF5 : STD_LOGIC; 
  signal Mtrien_ld_BUF5_OE : STD_LOGIC; 
  signal Mtrien_ld_BUF6 : STD_LOGIC; 
  signal Mtrien_ld_BUF6_OE : STD_LOGIC; 
  signal lclk_OBUF_BUF0 : STD_LOGIC; 
  signal led1_OBUF_BUF0 : STD_LOGIC; 
  signal sa_0_OBUF_BUF0 : STD_LOGIC; 
  signal sa_10_OBUF_BUF0 : STD_LOGIC; 
  signal sa_11_OBUF_BUF0 : STD_LOGIC; 
  signal sa_12_OBUF_BUF0 : STD_LOGIC; 
  signal sa_13_OBUF_BUF0 : STD_LOGIC; 
  signal sa_14_OBUF_BUF0 : STD_LOGIC; 
  signal sa_1_OBUF_BUF0 : STD_LOGIC; 
  signal sa_2_OBUF_BUF0 : STD_LOGIC; 
  signal sa_3_OBUF_BUF0 : STD_LOGIC; 
  signal sa_4_OBUF_BUF0 : STD_LOGIC; 
  signal sa_5_OBUF_BUF0 : STD_LOGIC; 
  signal sa_6_OBUF_BUF0 : STD_LOGIC; 
  signal sa_7_OBUF_BUF0 : STD_LOGIC; 
  signal sa_8_OBUF_BUF0 : STD_LOGIC; 
  signal sa_9_OBUF_BUF0 : STD_LOGIC; 
  signal Mtridata_ld_7_Q : STD_LOGIC; 
  signal Mtridata_ld_7_BUF0 : STD_LOGIC; 
  signal Mtridata_ld_7_BUF1 : STD_LOGIC; 
  signal Mtridata_ld_7_BUF2 : STD_LOGIC; 
  signal Mtridata_ld_7_BUF3 : STD_LOGIC; 
  signal Mtridata_ld_7_BUF4 : STD_LOGIC; 
  signal Mtridata_ld_7_BUF5 : STD_LOGIC; 
  signal Mtridata_ld_7_BUF6 : STD_LOGIC; 
  signal Mtridata_ld_7_BUF7 : STD_LOGIC; 
  signal led2_OBUF_Q : STD_LOGIC; 
  signal Mtrien_ld_Q_0 : STD_LOGIC; 
  signal Mtrien_ld : STD_LOGIC; 
  signal Mtrien_ld_BUFOE_OUT : STD_LOGIC; 
  signal Mtrien_ld_TRST : STD_LOGIC; 
  signal Mtrien_ld_D : STD_LOGIC; 
  signal Gnd : STD_LOGIC; 
  signal PRLD : STD_LOGIC; 
  signal Vcc : STD_LOGIC; 
  signal Mtrien_ld_D1 : STD_LOGIC; 
  signal Mtrien_ld_D2 : STD_LOGIC; 
  signal Mtrien_ld_D2_PT_0 : STD_LOGIC; 
  signal Mtrien_ld_D2_PT_1 : STD_LOGIC; 
  signal oe_OBUF_Q : STD_LOGIC; 
  signal oe_OBUF_D : STD_LOGIC; 
  signal oe_OBUF_CE : STD_LOGIC; 
  signal oe_OBUF_D1 : STD_LOGIC; 
  signal oe_OBUF_D2 : STD_LOGIC; 
  signal ready_OBUF_Q : STD_LOGIC; 
  signal ready_OBUF_UIM : STD_LOGIC; 
  signal ready_OBUF_D : STD_LOGIC; 
  signal ready_OBUF_D1 : STD_LOGIC; 
  signal ready_OBUF_D2 : STD_LOGIC; 
  signal ready_OBUF_D2_PT_0 : STD_LOGIC; 
  signal ready_OBUF_D2_PT_1 : STD_LOGIC; 
  signal we_OBUF_Q : STD_LOGIC; 
  signal we_OBUF_D : STD_LOGIC; 
  signal we_OBUF_CE : STD_LOGIC; 
  signal we_OBUF_D1 : STD_LOGIC; 
  signal we_OBUF_D2 : STD_LOGIC; 
  signal lint_OBUF_Q_1 : STD_LOGIC; 
  signal lint_OBUF : STD_LOGIC; 
  signal lint_OBUF_D : STD_LOGIC; 
  signal lint_OBUF_D1 : STD_LOGIC; 
  signal lint_OBUF_D2 : STD_LOGIC; 
  signal int : STD_LOGIC; 
  signal int_Q : STD_LOGIC; 
  signal int_RSTF : STD_LOGIC; 
  signal int_tsimcreated_prld_Q : STD_LOGIC; 
  signal int_D : STD_LOGIC; 
  signal int_D1 : STD_LOGIC; 
  signal int_D2 : STD_LOGIC; 
  signal int4 : STD_LOGIC; 
  signal int2_Q : STD_LOGIC; 
  signal int2 : STD_LOGIC; 
  signal int2_D : STD_LOGIC; 
  signal int2_D1 : STD_LOGIC; 
  signal int2_D2 : STD_LOGIC; 
  signal int3_Q : STD_LOGIC; 
  signal int3 : STD_LOGIC; 
  signal int3_D : STD_LOGIC; 
  signal int3_D1 : STD_LOGIC; 
  signal int3_D2 : STD_LOGIC; 
  signal int4_Q : STD_LOGIC; 
  signal int4_D : STD_LOGIC; 
  signal int4_D1 : STD_LOGIC; 
  signal int4_D2 : STD_LOGIC; 
  signal lholda_OBUF_Q : STD_LOGIC; 
  signal lholda_OBUF_D : STD_LOGIC; 
  signal lholda_OBUF_D1 : STD_LOGIC; 
  signal lholda_OBUF_D2 : STD_LOGIC; 
  signal Mtrien_ld_BUF0_Q : STD_LOGIC; 
  signal Mtrien_ld_BUF0_BUFOE_OUT : STD_LOGIC; 
  signal Mtrien_ld_BUF0_TRST : STD_LOGIC; 
  signal Mtrien_ld_BUF0_D : STD_LOGIC; 
  signal Mtrien_ld_BUF0_D1 : STD_LOGIC; 
  signal Mtrien_ld_BUF0_D2 : STD_LOGIC; 
  signal Mtrien_ld_BUF1_Q : STD_LOGIC; 
  signal Mtrien_ld_BUF1_BUFOE_OUT : STD_LOGIC; 
  signal Mtrien_ld_BUF1_TRST : STD_LOGIC; 
  signal Mtrien_ld_BUF1_D : STD_LOGIC; 
  signal Mtrien_ld_BUF1_D1 : STD_LOGIC; 
  signal Mtrien_ld_BUF1_D2 : STD_LOGIC; 
  signal Mtrien_ld_BUF2_Q : STD_LOGIC; 
  signal Mtrien_ld_BUF2_BUFOE_OUT : STD_LOGIC; 
  signal Mtrien_ld_BUF2_TRST : STD_LOGIC; 
  signal Mtrien_ld_BUF2_D : STD_LOGIC; 
  signal Mtrien_ld_BUF2_D1 : STD_LOGIC; 
  signal Mtrien_ld_BUF2_D2 : STD_LOGIC; 
  signal Mtrien_ld_BUF3_Q : STD_LOGIC; 
  signal Mtrien_ld_BUF3_BUFOE_OUT : STD_LOGIC; 
  signal Mtrien_ld_BUF3_TRST : STD_LOGIC; 
  signal Mtrien_ld_BUF3_D : STD_LOGIC; 
  signal Mtrien_ld_BUF3_D1 : STD_LOGIC; 
  signal Mtrien_ld_BUF3_D2 : STD_LOGIC; 
  signal Mtrien_ld_BUF4_Q : STD_LOGIC; 
  signal Mtrien_ld_BUF4_BUFOE_OUT : STD_LOGIC; 
  signal Mtrien_ld_BUF4_TRST : STD_LOGIC; 
  signal Mtrien_ld_BUF4_D : STD_LOGIC; 
  signal Mtrien_ld_BUF4_D1 : STD_LOGIC; 
  signal Mtrien_ld_BUF4_D2 : STD_LOGIC; 
  signal Mtrien_ld_BUF5_Q : STD_LOGIC; 
  signal Mtrien_ld_BUF5_BUFOE_OUT : STD_LOGIC; 
  signal Mtrien_ld_BUF5_TRST : STD_LOGIC; 
  signal Mtrien_ld_BUF5_D : STD_LOGIC; 
  signal Mtrien_ld_BUF5_D1 : STD_LOGIC; 
  signal Mtrien_ld_BUF5_D2 : STD_LOGIC; 
  signal Mtrien_ld_BUF6_Q : STD_LOGIC; 
  signal Mtrien_ld_BUF6_BUFOE_OUT : STD_LOGIC; 
  signal Mtrien_ld_BUF6_TRST : STD_LOGIC; 
  signal Mtrien_ld_BUF6_D : STD_LOGIC; 
  signal Mtrien_ld_BUF6_D1 : STD_LOGIC; 
  signal Mtrien_ld_BUF6_D2 : STD_LOGIC; 
  signal lclk_OBUF_BUF0_Q : STD_LOGIC; 
  signal lclk_OBUF_BUF0_D : STD_LOGIC; 
  signal lclk_OBUF_BUF0_D1 : STD_LOGIC; 
  signal lclk_OBUF_BUF0_D2 : STD_LOGIC; 
  signal led1_OBUF_BUF0_Q : STD_LOGIC; 
  signal led1_OBUF_BUF0_D : STD_LOGIC; 
  signal led1_OBUF_BUF0_D1 : STD_LOGIC; 
  signal led1_OBUF_BUF0_D2 : STD_LOGIC; 
  signal sa_0_OBUF_BUF0_Q : STD_LOGIC; 
  signal sa_0_OBUF_BUF0_D : STD_LOGIC; 
  signal sa_0_OBUF_BUF0_D1 : STD_LOGIC; 
  signal sa_0_OBUF_BUF0_D2 : STD_LOGIC; 
  signal sa_10_OBUF_BUF0_Q : STD_LOGIC; 
  signal sa_10_OBUF_BUF0_D : STD_LOGIC; 
  signal sa_10_OBUF_BUF0_D1 : STD_LOGIC; 
  signal sa_10_OBUF_BUF0_D2 : STD_LOGIC; 
  signal sa_11_OBUF_BUF0_Q : STD_LOGIC; 
  signal sa_11_OBUF_BUF0_D : STD_LOGIC; 
  signal sa_11_OBUF_BUF0_D1 : STD_LOGIC; 
  signal sa_11_OBUF_BUF0_D2 : STD_LOGIC; 
  signal sa_12_OBUF_BUF0_Q : STD_LOGIC; 
  signal sa_12_OBUF_BUF0_D : STD_LOGIC; 
  signal sa_12_OBUF_BUF0_D1 : STD_LOGIC; 
  signal sa_12_OBUF_BUF0_D2 : STD_LOGIC; 
  signal sa_13_OBUF_BUF0_Q : STD_LOGIC; 
  signal sa_13_OBUF_BUF0_D : STD_LOGIC; 
  signal sa_13_OBUF_BUF0_D1 : STD_LOGIC; 
  signal sa_13_OBUF_BUF0_D2 : STD_LOGIC; 
  signal sa_14_OBUF_BUF0_Q : STD_LOGIC; 
  signal sa_14_OBUF_BUF0_D : STD_LOGIC; 
  signal sa_14_OBUF_BUF0_D1 : STD_LOGIC; 
  signal sa_14_OBUF_BUF0_D2 : STD_LOGIC; 
  signal sa_1_OBUF_BUF0_Q : STD_LOGIC; 
  signal sa_1_OBUF_BUF0_D : STD_LOGIC; 
  signal sa_1_OBUF_BUF0_D1 : STD_LOGIC; 
  signal sa_1_OBUF_BUF0_D2 : STD_LOGIC; 
  signal sa_2_OBUF_BUF0_Q : STD_LOGIC; 
  signal sa_2_OBUF_BUF0_D : STD_LOGIC; 
  signal sa_2_OBUF_BUF0_D1 : STD_LOGIC; 
  signal sa_2_OBUF_BUF0_D2 : STD_LOGIC; 
  signal sa_3_OBUF_BUF0_Q : STD_LOGIC; 
  signal sa_3_OBUF_BUF0_D : STD_LOGIC; 
  signal sa_3_OBUF_BUF0_D1 : STD_LOGIC; 
  signal sa_3_OBUF_BUF0_D2 : STD_LOGIC; 
  signal sa_4_OBUF_BUF0_Q : STD_LOGIC; 
  signal sa_4_OBUF_BUF0_D : STD_LOGIC; 
  signal sa_4_OBUF_BUF0_D1 : STD_LOGIC; 
  signal sa_4_OBUF_BUF0_D2 : STD_LOGIC; 
  signal sa_5_OBUF_BUF0_Q : STD_LOGIC; 
  signal sa_5_OBUF_BUF0_D : STD_LOGIC; 
  signal sa_5_OBUF_BUF0_D1 : STD_LOGIC; 
  signal sa_5_OBUF_BUF0_D2 : STD_LOGIC; 
  signal sa_6_OBUF_BUF0_Q : STD_LOGIC; 
  signal sa_6_OBUF_BUF0_D : STD_LOGIC; 
  signal sa_6_OBUF_BUF0_D1 : STD_LOGIC; 
  signal sa_6_OBUF_BUF0_D2 : STD_LOGIC; 
  signal sa_7_OBUF_BUF0_Q : STD_LOGIC; 
  signal sa_7_OBUF_BUF0_D : STD_LOGIC; 
  signal sa_7_OBUF_BUF0_D1 : STD_LOGIC; 
  signal sa_7_OBUF_BUF0_D2 : STD_LOGIC; 
  signal sa_8_OBUF_BUF0_Q : STD_LOGIC; 
  signal sa_8_OBUF_BUF0_D : STD_LOGIC; 
  signal sa_8_OBUF_BUF0_D1 : STD_LOGIC; 
  signal sa_8_OBUF_BUF0_D2 : STD_LOGIC; 
  signal sa_9_OBUF_BUF0_Q : STD_LOGIC; 
  signal sa_9_OBUF_BUF0_D : STD_LOGIC; 
  signal sa_9_OBUF_BUF0_D1 : STD_LOGIC; 
  signal sa_9_OBUF_BUF0_D2 : STD_LOGIC; 
  signal Mtridata_ld_7_Q_2 : STD_LOGIC; 
  signal Mtridata_ld_7_D : STD_LOGIC; 
  signal Mtridata_ld_7_D1 : STD_LOGIC; 
  signal Mtridata_ld_7_D2 : STD_LOGIC; 
  signal Mtridata_ld_7_BUF0_Q : STD_LOGIC; 
  signal Mtridata_ld_7_BUF0_D : STD_LOGIC; 
  signal Mtridata_ld_7_BUF0_D1 : STD_LOGIC; 
  signal Mtridata_ld_7_BUF0_D2 : STD_LOGIC; 
  signal Mtridata_ld_7_BUF1_Q : STD_LOGIC; 
  signal Mtridata_ld_7_BUF1_D : STD_LOGIC; 
  signal Mtridata_ld_7_BUF1_D1 : STD_LOGIC; 
  signal Mtridata_ld_7_BUF1_D2 : STD_LOGIC; 
  signal Mtridata_ld_7_BUF2_Q : STD_LOGIC; 
  signal Mtridata_ld_7_BUF2_D : STD_LOGIC; 
  signal Mtridata_ld_7_BUF2_D1 : STD_LOGIC; 
  signal Mtridata_ld_7_BUF2_D2 : STD_LOGIC; 
  signal Mtridata_ld_7_BUF3_Q : STD_LOGIC; 
  signal Mtridata_ld_7_BUF3_D : STD_LOGIC; 
  signal Mtridata_ld_7_BUF3_D1 : STD_LOGIC; 
  signal Mtridata_ld_7_BUF3_D2 : STD_LOGIC; 
  signal Mtridata_ld_7_BUF4_Q : STD_LOGIC; 
  signal Mtridata_ld_7_BUF4_D : STD_LOGIC; 
  signal Mtridata_ld_7_BUF4_D1 : STD_LOGIC; 
  signal Mtridata_ld_7_BUF4_D2 : STD_LOGIC; 
  signal Mtridata_ld_7_BUF5_Q : STD_LOGIC; 
  signal Mtridata_ld_7_BUF5_D : STD_LOGIC; 
  signal Mtridata_ld_7_BUF5_D1 : STD_LOGIC; 
  signal Mtridata_ld_7_BUF5_D2 : STD_LOGIC; 
  signal Mtridata_ld_7_BUF6_Q : STD_LOGIC; 
  signal Mtridata_ld_7_BUF6_D : STD_LOGIC; 
  signal Mtridata_ld_7_BUF6_D1 : STD_LOGIC; 
  signal Mtridata_ld_7_BUF6_D2 : STD_LOGIC; 
  signal Mtridata_ld_7_BUF7_Q : STD_LOGIC; 
  signal Mtridata_ld_7_BUF7_D : STD_LOGIC; 
  signal Mtridata_ld_7_BUF7_D1 : STD_LOGIC; 
  signal Mtridata_ld_7_BUF7_D2 : STD_LOGIC; 
  signal led2_OBUF_Q_3 : STD_LOGIC; 
  signal led2_OBUF_D : STD_LOGIC; 
  signal led2_OBUF_D1 : STD_LOGIC; 
  signal led2_OBUF_D2 : STD_LOGIC; 
  signal NlwInverterSignal_Mtrien_ld_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Mtrien_ld_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Mtrien_ld_TRST_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Mtrien_ld_TRST_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_oe_OBUF_CE_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_oe_OBUF_CE_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_ready_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_ready_OBUF_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_we_OBUF_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_we_OBUF_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_we_OBUF_CE_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_we_OBUF_CE_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lint_OBUF_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lint_OBUF_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_int2_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_int2_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_int3_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_int3_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_int4_D2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_int4_D2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Mtrien_ld_BUF0_TRST_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Mtrien_ld_BUF0_TRST_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Mtrien_ld_BUF1_TRST_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Mtrien_ld_BUF1_TRST_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Mtrien_ld_BUF2_TRST_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Mtrien_ld_BUF2_TRST_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Mtrien_ld_BUF3_TRST_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Mtrien_ld_BUF3_TRST_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Mtrien_ld_BUF4_TRST_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Mtrien_ld_BUF4_TRST_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Mtrien_ld_BUF5_TRST_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Mtrien_ld_BUF5_TRST_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Mtrien_ld_BUF6_TRST_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Mtrien_ld_BUF6_TRST_IN1 : STD_LOGIC; 
begin
  lclk_OBUF_4 : X_BUF
    port map (
      I => main_clk,
      O => lclk_OBUF
    );
  FCLKIO_0_5 : X_BUF
    port map (
      I => main_clk,
      O => FCLKIO_0
    );
  cpld_IBUF_6 : X_BUF
    port map (
      I => cpld,
      O => cpld_IBUF
    );
  wr_IBUF_7 : X_BUF
    port map (
      I => wr,
      O => wr_IBUF
    );
  blast_IBUF_8 : X_BUF
    port map (
      I => blast,
      O => blast_IBUF
    );
  ads_IBUF_9 : X_BUF
    port map (
      I => ads,
      O => ads_IBUF
    );
  led1_OBUF_10 : X_BUF
    port map (
      I => onoffa,
      O => led1_OBUF
    );
  FCLKIO_1_11 : X_BUF
    port map (
      I => onoffa,
      O => FCLKIO_1
    );
  lhold_IBUF_12 : X_BUF
    port map (
      I => lhold,
      O => lhold_IBUF
    );
  sa_0_OBUF_13 : X_BUF
    port map (
      I => la(0),
      O => sa_0_OBUF
    );
  sa_10_OBUF_14 : X_BUF
    port map (
      I => la(10),
      O => sa_10_OBUF
    );
  sa_11_OBUF_15 : X_BUF
    port map (
      I => la(11),
      O => sa_11_OBUF
    );
  sa_12_OBUF_16 : X_BUF
    port map (
      I => la(12),
      O => sa_12_OBUF
    );
  sa_13_OBUF_17 : X_BUF
    port map (
      I => la(13),
      O => sa_13_OBUF
    );
  sa_14_OBUF_18 : X_BUF
    port map (
      I => la(14),
      O => sa_14_OBUF
    );
  sa_1_OBUF_19 : X_BUF
    port map (
      I => la(1),
      O => sa_1_OBUF
    );
  sa_2_OBUF_20 : X_BUF
    port map (
      I => la(2),
      O => sa_2_OBUF
    );
  sa_3_OBUF_21 : X_BUF
    port map (
      I => la(3),
      O => sa_3_OBUF
    );
  sa_4_OBUF_22 : X_BUF
    port map (
      I => la(4),
      O => sa_4_OBUF
    );
  sa_5_OBUF_23 : X_BUF
    port map (
      I => la(5),
      O => sa_5_OBUF
    );
  sa_6_OBUF_24 : X_BUF
    port map (
      I => la(6),
      O => sa_6_OBUF
    );
  sa_7_OBUF_25 : X_BUF
    port map (
      I => la(7),
      O => sa_7_OBUF
    );
  sa_8_OBUF_26 : X_BUF
    port map (
      I => la(8),
      O => sa_8_OBUF
    );
  sa_9_OBUF_27 : X_BUF
    port map (
      I => la(9),
      O => sa_9_OBUF
    );
  ld_7_Q : X_TRI
    port map (
      I => Mtrien_ld_Q,
      CTL => Mtrien_ld_OE,
      O => ld(7)
    );
  oe_28 : X_BUF
    port map (
      I => oe_OBUF,
      O => oe
    );
  ready_29 : X_BUF
    port map (
      I => ready_OBUF,
      O => ready
    );
  we_30 : X_BUF
    port map (
      I => we_OBUF,
      O => we
    );
  lint_31 : X_BUF
    port map (
      I => lint_OBUF_Q,
      O => lint
    );
  lholda_32 : X_BUF
    port map (
      I => lholda_OBUF,
      O => lholda
    );
  ld_6_Q : X_TRI
    port map (
      I => Mtrien_ld_BUF0,
      CTL => Mtrien_ld_BUF0_OE,
      O => ld(6)
    );
  ld_5_Q : X_TRI
    port map (
      I => Mtrien_ld_BUF1,
      CTL => Mtrien_ld_BUF1_OE,
      O => ld(5)
    );
  ld_4_Q : X_TRI
    port map (
      I => Mtrien_ld_BUF2,
      CTL => Mtrien_ld_BUF2_OE,
      O => ld(4)
    );
  ld_3_Q : X_TRI
    port map (
      I => Mtrien_ld_BUF3,
      CTL => Mtrien_ld_BUF3_OE,
      O => ld(3)
    );
  ld_2_Q : X_TRI
    port map (
      I => Mtrien_ld_BUF4,
      CTL => Mtrien_ld_BUF4_OE,
      O => ld(2)