ss.tbw

采用9054做为板卡与计算机通信的媒介

version 3
d:\study\pci\90541.vhd
a90541
VHDL
VHDL
ss.xwv
Clocked
-
-
1000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
main_clk
25000000
25000000
10000000
5000000
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
ads
main_clk
blast
main_clk
ce
main_clk
cpld
main_clk
la
main_clk
lclk
main_clk
ld
main_clk
led
main_clk
led1
main_clk
led2
main_clk
lhold
main_clk
lholda
main_clk
lint
main_clk
oe
main_clk
onoffa
main_clk
ready
main_clk
sa
main_clk
we
main_clk
wr
main_clk
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
ce_DIFF
lclk_DIFF
led1_DIFF
led2_DIFF
led_DIFF
lholda_DIFF
lint_DIFF
oe_DIFF
ready_DIFF
sa_DIFF
we_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
main_clk
ads
blast
cpld
lhold
onoffa
wr
la
ce
lclk
led1
led2
lholda
lint
oe
ready
we
led
sa
ld
SIGNAL_ORDER_END
-X-X-X-