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<h3 align='center'>Equations</h3>
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********** Mapped Logic **********
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ce <= '0';
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FDCPE_int: FDCPE port map (int,'1',onoffa,int_CLR,'0');
<br/> int_CLR <= (int AND int4);
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FDCPE_int2: FDCPE port map (int2,NOT lint,main_clk,'0','0');
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FDCPE_int3: FDCPE port map (int3,NOT int2,main_clk,'0','0');
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FDCPE_int4: FDCPE port map (int4,NOT int3,main_clk,'0','0');
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lclk <= main_clk;
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ld_I(0) <= ld(7);
<br/> ld(0) <= ld_I(0) when ld_OE(0) = '1' else 'Z';
<br/> ld_OE(0) <= NOT ld(7);
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ld_I(1) <= ld(7);
<br/> ld(1) <= ld_I(1) when ld_OE(1) = '1' else 'Z';
<br/> ld_OE(1) <= NOT ld(7);
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ld_I(2) <= ld(7);
<br/> ld(2) <= ld_I(2) when ld_OE(2) = '1' else 'Z';
<br/> ld_OE(2) <= NOT ld(7);
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ld_I(3) <= ld(7);
<br/> ld(3) <= ld_I(3) when ld_OE(3) = '1' else 'Z';
<br/> ld_OE(3) <= NOT ld(7);
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ld_I(4) <= ld(7);
<br/> ld(4) <= ld_I(4) when ld_OE(4) = '1' else 'Z';
<br/> ld_OE(4) <= NOT ld(7);
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ld_I(5) <= ld(7);
<br/> ld(5) <= ld_I(5) when ld_OE(5) = '1' else 'Z';
<br/> ld_OE(5) <= NOT ld(7);
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ld_I(6) <= ld(7);
<br/> ld(6) <= ld_I(6) when ld_OE(6) = '1' else 'Z';
<br/> ld_OE(6) <= NOT ld(7);
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FDCPE_ld7: FDCPE port map (ld_I(7),ld(7),main_clk,'0','0');
<br/> ld(7) <= ((NOT cpld)
<br/> OR (ld(7) AND wr));
<br/> ld(7) <= ld_I(7) when ld_OE(7) = '1' else 'Z';
<br/> ld_OE(7) <= NOT ld(7);
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led1 <= onoffa;
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led2 <= '1';
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led(0) <= '0';
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led(1) <= '0';
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led(2) <= '0';
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led(3) <= '0';
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led(4) <= '0';
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led(5) <= '0';
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led(6) <= '0';
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led(7) <= '0';
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FDCPE_lholda: FDCPE port map (lholda,lhold,main_clk,'0','0');
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FDCPE_lint: FDCPE port map (lint,NOT int,main_clk,'0','0');
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FDCPE_oe: FDCPE port map (oe,wr,main_clk,'0','0',NOT cpld);
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FDCPE_ready: FDCPE port map (ready,ready_D,main_clk,'0','0');
<br/> ready_D <= ((NOT blast)
<br/> OR (ready AND ads));
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sa(0) <= la(0);
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sa(1) <= la(1);
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sa(2) <= la(2);
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sa(3) <= la(3);
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sa(4) <= la(4);
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sa(5) <= la(5);
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sa(6) <= la(6);
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sa(7) <= la(7);
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sa(8) <= la(8);
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sa(9) <= la(9);
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sa(10) <= la(10);
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sa(11) <= la(11);
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sa(12) <= la(12);
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sa(13) <= la(13);
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sa(14) <= la(14);
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FDCPE_we: FDCPE port map (we,NOT wr,main_clk,'0','0',NOT cpld);
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Register Legend:
<br/> FDCPE (Q,D,C,CLR,PRE,CE);
<br/> FTCPE (Q,D,C,CLR,PRE,CE);
<br/> LDCP (Q,D,G,CLR,PRE);
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