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HTM
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cpldfit: version H.42 Xilinx Inc.
Fitter Report
Design Name: a90541 Date: 3-23-2007, 3:11PM
Device Used: XC95288XL-10-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
44 /288 ( 15%) 46 /1440 ( 3%) 35 /864 ( 4%) 10 /288 ( 3%) 42 /117 ( 36%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 5/18 3/54 8/90 3/ 8
FB2 5/18 3/54 8/90 5/10
FB3 0/18 0/54 0/90 0/ 5
FB4 2/18 3/54 2/90 1/ 6
FB5 3/18 3/54 3/90 3/ 8
FB6 3/18 5/54 4/90 3/ 8
FB7 0/18 0/54 0/90 0/ 4
FB8 1/18 0/54 0/90 1/ 5
FB9 4/18 3/54 3/90 4/ 9
FB10 5/18 4/54 4/90 5/10
FB11 2/18 0/54 0/90 2/ 7
FB12 1/18 1/54 1/90 1/ 6
FB13 2/18 0/54 0/90 2/ 6
FB14 3/18 3/54 5/90 3/ 8
FB15 4/18 4/54 4/90 4/ 9
FB16 4/18 3/54 4/90 3/ 8
----- ----- ----- -----
44/288 35/864 46/1440 40/117
* - Resource is exhausted
** Global Control Resources **
Signal 'main_clk' mapped onto global clock net GCK1.
Signal 'onoffa' mapped onto global clock net GCK2.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 20 20 | I/O : 58 109
Output : 40 40 | GCK/IO : 3 3
Bidirectional : 0 0 | GTS/IO : 1 4
GCK : 2 2 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 62 62
** Power Data **
There are 44 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************* Summary of Mapped Logic ************************
** 40 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
ld<5> 2 1 FB1_5 20 I/O O STD FAST
ld<4> 2 1 FB1_10 23 I/O O STD FAST
ld<3> 2 1 FB1_15 26 I/O O STD FAST
ld<2> 2 1 FB2_2 9 I/O O STD FAST
ld<1> 2 1 FB2_5 11 I/O O STD FAST
ld<0> 2 1 FB2_8 13 I/O O STD FAST
sa<10> 1 1 FB2_12 15 I/O O STD FAST
sa<11> 1 1 FB2_15 17 I/O O STD FAST
sa<6> 1 1 FB4_6 4 I/O O STD FAST
sa<7> 1 1 FB5_2 34 I/O O STD FAST
sa<8> 1 1 FB5_10 39 I/O O STD FAST
sa<9> 1 1 FB5_14 41 I/O O STD FAST
ready 2 3 FB6_2 135 I/O O STD FAST SET
sa<14> 1 1 FB6_5 137 I/O O STD FAST
sa<2> 1 1 FB6_8 139 I/O O STD FAST
ce 0 0 FB8_2 130 I/O O STD FAST
led<0> 0 0 FB9_2 50 I/O O STD FAST
led1 1 1 FB9_5 52 I/O O STD FAST
sa<13> 1 1 FB9_11 56 I/O O STD FAST
sa<12> 1 1 FB9_14 58 I/O O STD FAST
led<1> 0 0 FB10_2 117 I/O O STD FAST
lclk 1 1 FB10_5 119 I/O O STD FAST
lint 1 1 FB10_8 121 I/O O STD FAST RESET
sa<1> 1 1 FB10_11 125 I/O O STD FAST
sa<4> 1 1 FB10_14 128 I/O O STD FAST
led<3> 0 0 FB11_3 60 I/O O STD FAST
led2 0 0 FB11_12 68 I/O O STD FAST
sa<5> 1 1 FB12_2 110 I/O O STD FAST
led<4> 0 0 FB13_2 71 I/O O STD FAST
led<2> 0 0 FB13_14 76 I/O O STD FAST
ld<7> 3 3 FB14_3 100 I/O O STD FAST RESET
we 2 2 FB14_8 103 I/O O STD FAST RESET
led<5> 0 0 FB14_14 106 I/O O STD FAST
oe 2 2 FB15_2 79 I/O O STD FAST RESET
led<6> 0 0 FB15_8 81 I/O O STD FAST
lholda 1 1 FB15_11 83 I/O O STD FAST RESET
sa<0> 1 1 FB15_15 87 I/O O STD FAST
ld<6> 2 1 FB16_2 91 I/O O STD FAST
led<7> 0 0 FB16_6 94 I/O O STD FAST
sa<3> 1 1 FB16_11 97 I/O O STD FAST
** 4 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
int4 1 1 FB1_17 STD RESET
int3 1 1 FB1_18 STD RESET
int 1 2 FB4_18 STD RESET
int2 1 1 FB16_18 STD RESET
** 22 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
la<7> FB1_14 25 I/O I
la<10> FB2_3 10 I/O I
la<11> FB2_6 12 I/O I
main_clk FB3_10 30~ GCK/I/O GCK/I
onoffa FB3_14 32~ GCK/I/O GCK/I
la<3> FB4_12 6 GTS/I/O I
la<13> FB5_5 35 I/O I
la<8> FB5_8 38 GCK/I/O I
la<0> FB5_12 40 I/O I
la<9> FB5_17 44 I/O I
la<2> FB6_6 138 I/O I
wr FB8_5 132 I/O I
la<14> FB8_10 134 I/O I
la<1> FB9_17 59 I/O I
blast FB10_3 118 I/O I
ads FB11_10 64 I/O I
cpld FB13_15 77 I/O I
lhold FB14_10 104 I/O I
la<5> FB14_11 105 I/O I
la<12> FB15_12 85 I/O I
la<6> FB15_17 88 I/O I
la<4> FB16_5 93 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 3/51
Number of signals used by logic mapping into function block: 3
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 (b)
(unused) 0 0 0 5 FB1_2 (b)
(unused) 0 0 0 5 FB1_3 (b)
(unused) 0 0 0 5 FB1_4 (b)
ld<5> 2 0 0 3 FB1_5 20 I/O O
(unused) 0 0 0 5 FB1_6 21 I/O
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 22 I/O
(unused) 0 0 0 5 FB1_9 (b)
ld<4> 2 0 0 3 FB1_10 23 I/O O
(unused) 0 0 0 5 FB1_11 (b)
(unused) 0 0 0 5 FB1_12 24 I/O
(unused) 0 0 0 5 FB1_13 (b)
(unused) 0 0 0 5 FB1_14 25 I/O I
ld<3> 2 0 0 3 FB1_15 26 I/O O
(unused) 0 0 0 5 FB1_16 (b)
int4 1 0 0 4 FB1_17 27 I/O (b)
int3 1 0 0 4 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: int2 2: int3 3: ld<7>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
ld<5> ..X..................................... 1
ld<4> ..X..................................... 1
ld<3> ..X..................................... 1
int4 .X...................................... 1
int3 X....................................... 1
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 3/51
Number of signals used by logic mapping into function block: 3
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 (b)
ld<2> 2 0 0 3 FB2_2 9 I/O O
(unused) 0 0 0 5 FB2_3 10 I/O I
(unused) 0 0 0 5 FB2_4 (b)
ld<1> 2 0 0 3 FB2_5 11 I/O O
(unused) 0 0 0 5 FB2_6 12 I/O I
(unused) 0 0 0 5 FB2_7 (b)
ld<0> 2 0 0 3 FB2_8 13 I/O O
(unused) 0 0 0 5 FB2_9 (b)
(unused) 0 0 0 5 FB2_10 14 I/O
(unused) 0 0 0 5 FB2_11 (b)
sa<10> 1 0 0 4 FB2_12 15 I/O O
(unused) 0 0 0 5 FB2_13 (b)
(unused) 0 0 0 5 FB2_14 16 I/O
sa<11> 1 0 0 4 FB2_15 17 I/O O
(unused) 0 0 0 5 FB2_16 (b)
(unused) 0 0 0 5 FB2_17 19 I/O
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: ld<7> 2: la<10> 3: la<11>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
ld<2> X....................................... 1
ld<1> X....................................... 1
ld<0> X....................................... 1
sa<10> .X...................................... 1
sa<11> ..X..................................... 1
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 0/54
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
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