led_timesim.vhd

采用9054做为板卡与计算机通信的媒介

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: H.42
--  \   \         Application: netgen
--  /   /         Filename: led_timesim.vhd
-- /___/   /\     Timestamp: Thu Mar 15 21:06:16 2007
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim led.nga led_timesim.vhd 
-- Device	: XC95288XL-10-TQ144 (Speed File: Version 3.0)
-- Input file	: led.nga
-- Output file	: led_timesim.vhd
-- # of Entities	: 1
-- Design Name	: led.nga
-- Xilinx	: D:/tools/ISE7.1
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Verification Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity led is
  port (
    main_clk : in STD_LOGIC := 'X'; 
    lclk : out STD_LOGIC; 
    led1 : out STD_LOGIC; 
    led2 : out STD_LOGIC 
  );
end led;

architecture Structure of led is
  signal lclk_OBUF : STD_LOGIC; 
  signal lclk_OBUF_BUF0 : STD_LOGIC; 
  signal led1_OBUF : STD_LOGIC; 
  signal led2_OBUF : STD_LOGIC; 
  signal lclk_OBUF_BUF0_Q : STD_LOGIC; 
  signal lclk_OBUF_BUF0_D : STD_LOGIC; 
  signal lclk_OBUF_BUF0_D1 : STD_LOGIC; 
  signal lclk_OBUF_BUF0_D2 : STD_LOGIC; 
  signal led1_OBUF_Q : STD_LOGIC; 
  signal led1_OBUF_D : STD_LOGIC; 
  signal led1_OBUF_D1 : STD_LOGIC; 
  signal led1_OBUF_D2 : STD_LOGIC; 
  signal led2_OBUF_Q : STD_LOGIC; 
  signal led2_OBUF_D : STD_LOGIC; 
  signal led2_OBUF_D1 : STD_LOGIC; 
  signal led2_OBUF_D2 : STD_LOGIC; 
begin
  lclk_OBUF_0 : X_BUF
    port map (
      I => main_clk,
      O => lclk_OBUF
    );
  lclk_1 : X_BUF
    port map (
      I => lclk_OBUF_BUF0,
      O => lclk
    );
  led1_2 : X_BUF
    port map (
      I => led1_OBUF,
      O => led1
    );
  led2_3 : X_BUF
    port map (
      I => led2_OBUF,
      O => led2
    );
  lclk_OBUF_BUF0_4 : X_BUF
    port map (
      I => lclk_OBUF_BUF0_Q,
      O => lclk_OBUF_BUF0
    );
  lclk_OBUF_BUF0_Q_5 : X_BUF
    port map (
      I => lclk_OBUF_BUF0_D,
      O => lclk_OBUF_BUF0_Q
    );
  lclk_OBUF_BUF0_D_6 : X_XOR2
    port map (
      I0 => lclk_OBUF_BUF0_D1,
      I1 => lclk_OBUF_BUF0_D2,
      O => lclk_OBUF_BUF0_D
    );
  lclk_OBUF_BUF0_D1_7 : X_ZERO
    port map (
      O => lclk_OBUF_BUF0_D1
    );
  lclk_OBUF_BUF0_D2_8 : X_AND2
    port map (
      I0 => lclk_OBUF,
      I1 => lclk_OBUF,
      O => lclk_OBUF_BUF0_D2
    );
  led1_OBUF_9 : X_BUF
    port map (
      I => led1_OBUF_Q,
      O => led1_OBUF
    );
  led1_OBUF_Q_10 : X_BUF
    port map (
      I => led1_OBUF_D,
      O => led1_OBUF_Q
    );
  led1_OBUF_D_11 : X_XOR2
    port map (
      I0 => led1_OBUF_D1,
      I1 => led1_OBUF_D2,
      O => led1_OBUF_D
    );
  led1_OBUF_D1_12 : X_ZERO
    port map (
      O => led1_OBUF_D1
    );
  led1_OBUF_D2_13 : X_ZERO
    port map (
      O => led1_OBUF_D2
    );
  led2_OBUF_14 : X_BUF
    port map (
      I => led2_OBUF_Q,
      O => led2_OBUF
    );
  led2_OBUF_Q_15 : X_BUF
    port map (
      I => led2_OBUF_D,
      O => led2_OBUF_Q
    );
  led2_OBUF_D_16 : X_XOR2
    port map (
      I0 => led2_OBUF_D1,
      I1 => led2_OBUF_D2,
      O => led2_OBUF_D
    );
  led2_OBUF_D1_17 : X_ZERO
    port map (
      O => led2_OBUF_D1
    );
  led2_OBUF_D2_18 : X_ONE
    port map (
      O => led2_OBUF_D2
    );

end Structure;