90541.syr

来自「采用9054做为板卡与计算机通信的媒介」· SYR 代码 · 共 84 行

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.22 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
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--> Reading design: 90541.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "90541.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "90541"
Output Format                      : NGC
Target Device                      : xc9500xl

---- Source Options
Top Module Name                    : 90541
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain

---- Other Options
lso                                : 90541.lso
verilog2001                        : YES
safe_implementation                : No
Clock Enable                       : YES
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3498 - No primary, secondary unit in the file "D:/study/PCI/90541.vhd. Ignore this file from project file "90541_vhdl.prj".

=========================================================================
*                            HDL Analysis                               *
=========================================================================
ERROR:HDLParsers:340 - "D:/study/PCI/90541.vhd" Entity <90541> does not exist in library <work>.
ERROR:Xst:1867 - Entity <90541> not found, Recompile it.
--> 

Total memory usage is 77144 kilobytes

Number of errors   :    2 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)