2407a.h

DSP TMS320LF2407A 转速闭环控制系统

/*************************************************************************
/* File name: 2407A.h
/*
/* Description: 240x register definitions, Bit codes for BIT instruction
/*************************************************************************

/* 240x CPU core registers*/

volatile unsigned int *IMR 	=	(volatile unsigned int *)0x0004;	/* Interrupt Mask Register*/
volatile unsigned int *GREG =   (volatile unsigned int *)0x0005;
volatile unsigned int *IFR 	=	(volatile unsigned int *)0x0006;	/* Interrupt Flag Register*/

/* System configuration and interrupt registers*/

volatile unsigned int *SCSR1 	=	(volatile unsigned int *)0x7018;	/* System Control & Status register. 1 */
volatile unsigned int *SCSR2 	=	(volatile unsigned int *)0x7019;	/* System Control & Status register. 2*/
volatile unsigned int *DINR 	=	(volatile unsigned int *)0x701C;	/* Device Identification Number register. */
volatile unsigned int *PIVR 	=	(volatile unsigned int *)0x701E;	/* Peripheral Interrupt Vector register. */
volatile unsigned int *PIRQR0 	=	(volatile unsigned int *)0x7010;	/* Peripheral Interrupt Request register 0*/
volatile unsigned int *PIRQR1 	=	(volatile unsigned int *)0x7011;	/* Peripheral Interrupt Request register 1*/
volatile unsigned int *PIRQR2 	=	(volatile unsigned int *)0x7012;	/* Peripheral Interrupt Request register 2*/
volatile unsigned int *PIACKR0 	=	(volatile unsigned int *)0x7014;	/* Peripheral Interrupt Acknowledge register 0 */
volatile unsigned int *PIACKR1 	=	(volatile unsigned int *)0x7015;	/* Peripheral Interrupt Acknowledge register 1 */
volatile unsigned int *PIACKR2 	=	(volatile unsigned int *)0x7016;	/* Peripheral Interrupt Acknowledge register 2*/

/* External interrupt configuration registers */

volatile unsigned int *XINT1CR 	=	(volatile unsigned int *)0x7070;	/* External interrupt 1 control register*/
volatile unsigned int *XINT2CR 	=	(volatile unsigned int *)0x7071;	/* External interrupt 2 control register*/

/* Digital I/O registers*/

volatile unsigned int *MCRA      =(volatile unsigned int *)0x7090;	/* I/O Mux Control Register A*/
volatile unsigned int *MCRB 	=	(volatile unsigned int *)0x7092;	/* I/O Mux Control Register B*/
volatile unsigned int *MCRC 	=	(volatile unsigned int *)0x7094;	/* I/O Mux Control Register C*/
volatile unsigned int *PADATDIR 	=	(volatile unsigned int *)0x7098;	/* I/O port A Data & Direction register*/
volatile unsigned int *PBDATDIR 	=	(volatile unsigned int *)0x709A;	/* I/O port B Data & Direction register*/
volatile unsigned int *PCDATDIR 	=	(volatile unsigned int *)0x709C;	/* I/O port C Data & Direction register*/
volatile unsigned int *PDDATDIR 	=	(volatile unsigned int *)0x709E;	/* I/O port D Data & Direction register*/
volatile unsigned int *PEDATDIR 	=	(volatile unsigned int *)0x7095;	/* I/O port E Data & Direction register*/
volatile unsigned int *PFDATDIR 	=	(volatile unsigned int *)0x7096;	/* I/O port F Data & Direction register*/

/* Watchdog (WD) registers*/

volatile unsigned int *WDCNTR 		=	(volatile unsigned int *)0x7023;	/* WD Counter register */
volatile unsigned int *WDKEY 		=	(volatile unsigned int *)0x7025;	/* WD Key register*/
volatile unsigned int *WDCR         =(volatile unsigned int *)0x7029;
/* ADC registers*/

volatile unsigned int *ADCTRL1 	=	(volatile unsigned int *)0x70A0;	/* ADC Control register 1*/
volatile unsigned int *ADCTRL2 	=	(volatile unsigned int *)0x70A1;	/* ADC Control register 2*/
volatile unsigned int *MAXCONV 	=	(volatile unsigned int *)0x70A2;	/* Maximum conversion channels register*/
volatile unsigned int *CHSELSEQ1	=	(volatile unsigned int *)0x70A3;	/* Channel select Sequencing control register 1*/
volatile unsigned int *CHSELSEQ2 =	(volatile unsigned int *)0x70A4;	/* Channel select Sequencing control register 2*/
volatile unsigned int *CHSELSEQ3 =	(volatile unsigned int *)0x70A5;	/* Channel select Sequencing control register 3*/
volatile unsigned int *CHSELSEQ4 =	(volatile unsigned int *)0x70A6;	/* Channel select Sequencing control register 4*/
volatile unsigned int *AUTO_SEQ_SR =	(volatile unsigned int *)0x70A7;	/* Auto杝equence status register*/
volatile unsigned int *RESULT0 	=	(volatile unsigned int *)0x70A8;	/* Conversion result buffer register 0*/
volatile unsigned int *RESULT1 	=	(volatile unsigned int *)0x70A9;	/* Conversion result buffer register 1*/
volatile unsigned int *RESULT2 	=	(volatile unsigned int *)0x70Aa;	/* Conversion result buffer register 2*/
volatile unsigned int *RESULT3 	=	(volatile unsigned int *)0x70Ab;	/* Conversion result buffer register 3 */
volatile unsigned int *RESULT4 	=	(volatile unsigned int *)0x70Ac;	/* Conversion result buffer register 4*/
volatile unsigned int *RESULT5 	=	(volatile unsigned int *)0x70Ad;	/* Conversion result buffer register 5*/
volatile unsigned int *RESULT6 	=	(volatile unsigned int *)0x70Ae;	/* Conversion result buffer register 6*/
volatile unsigned int *RESULT7 	=	(volatile unsigned int *)0x70Af;	/* Conversion result buffer register 7*/
volatile unsigned int *RESULT8 	=	(volatile unsigned int *)0x70B0;	/* Conversion result buffer register 8*/
volatile unsigned int *RESULT9 	=	(volatile unsigned int *)0x70B1;	/* Conversion result buffer register 9 */
volatile unsigned int *RESULT10 	=	(volatile unsigned int *)0x70B2;	/* Conversion result buffer register 10*/
volatile unsigned int *RESULT11 	=	(volatile unsigned int *)0x70B3;	/* Conversion result buffer register 11*/
volatile unsigned int *RESULT12 	=	(volatile unsigned int *)0x70B4;	/* Conversion result buffer register 12*/
volatile unsigned int *RESULT13 	=	(volatile unsigned int *)0x70B5;	/* Conversion result buffer register 13*/
volatile unsigned int *RESULT14 	=	(volatile unsigned int *)0x70B6;	/* Conversion result buffer register 14*/
volatile unsigned int *RESULT15 	=	(volatile unsigned int *)0x70B7;	/* Conversion result buffer register 15*/
volatile unsigned int *CALIBRATION 	=	(volatile unsigned int *)0x70B8;	/* Calib result, used to correct*/
			 	/* subsequent conversions*/



/* SCI registers*/

volatile unsigned int *SCICCR 	=	(volatile unsigned int *)0x7050;	/* SCI Communication control register */
volatile unsigned int *SCICTL1 	=	(volatile unsigned int *)0x7051;	/* SCI Control register 1*/
volatile unsigned int *SCIHBAUD 	=	(volatile unsigned int *)0x7052;	/* SCI Baud Rate MS byte register */
volatile unsigned int *SCILBAUD 	=	(volatile unsigned int *)0x7053;	/* SCI Baud Rate LS byte register*/
volatile unsigned int *SCICTL2 	=	(volatile unsigned int *)0x7054;	/* SCI Control register 2*/
volatile unsigned int *SCIRXST 	=	(volatile unsigned int *)0x7055;	/* SCI Receiver Status register*/
volatile unsigned int *SCIRXEMU 	=	(volatile unsigned int *)0x7056;	/* SCI Emulation Data Buffer register */
volatile unsigned int *SCIRXBUF 	=	(volatile unsigned int *)0x7057;	/* SCI Receiver Data buffer register*/
volatile unsigned int *SCITXBUF 	=	(volatile unsigned int *)0x7059;	/* SCI Transmit Data buffer register*/
volatile unsigned int *SCIPRI 	=	(volatile unsigned int *)0x705F;	/* SCI Priority control register*/


/* Event Manager A (EVA) registers*/

volatile unsigned int *GPTCONA 	=	(volatile unsigned int *)0x7400;	/* GP Timer control register A*/
volatile unsigned int *T1CNT 	=	(volatile unsigned int *)0x7401;	/* GP Timer 1 counter register*/
volatile unsigned int *T1CMPR 	=	(volatile unsigned int *)0x7402;	/* GP Timer 1 compare register*/
volatile unsigned int *T1PR 	=	(volatile unsigned int *)0x7403;	/* GP Timer 1 period register*/
volatile unsigned int *T1CON 	=	(volatile unsigned int *)0x7404;	/* GP Timer 1 control register*/
volatile unsigned int *T2CNT 	=	(volatile unsigned int *)0x7405;	/* GP Timer 2 counter register*/
volatile unsigned int *T2CMPR 	=	(volatile unsigned int *)0x7406;	/* GP Timer 2 compare register*/
volatile unsigned int *T2PR 	=	(volatile unsigned int *)0x7407;	/* GP Timer 2 period register*/
volatile unsigned int *T2CON 	=	(volatile unsigned int *)0x7408;	/* GP Timer 2 control register*/

volatile unsigned int *COMCONA 	=	(volatile unsigned int *)0x7411;	/* Compare control register A */
volatile unsigned int *ACTRA 	=	(volatile unsigned int *)0x7413;	/* Full compare Action control register A*/
volatile unsigned int *DBTCONA 	=	(volatile unsigned int *)0x7415;	/* Dead朾and timer control register A */

volatile unsigned int *CMPR1 	=	(volatile unsigned int *)0x7417;	/* Full compare unit compare register1 */
volatile unsigned int *CMPR2 	=	(volatile unsigned int *)0x7418;	/* Full compare unit compare register2 */
volatile unsigned int *CMPR3 	=	(volatile unsigned int *)0x7419;	/* Full compare unit compare register3 */

volatile unsigned int *CAPCONA 	=	(volatile unsigned int *)0x7420;	/* Capture control register A*/
volatile unsigned int *CAPFIFOA 	=	(volatile unsigned int *)0x7422;	/* Capture FIFO status register A */

volatile unsigned int *CAP1FIFO 	=	(volatile unsigned int *)0x7423;	/* Capture Channel 1 FIFO Top*/
volatile unsigned int *CAP2FIFO 	=	(volatile unsigned int *)0x7424;	/* Capture Channel 2 FIFO Top*/
volatile unsigned int *CAP3FIFO 	=	(volatile unsigned int *)0x7425;	/* Capture Channel 3 FIFO Top*/

volatile unsigned int *CAP1FBOT 	=	(volatile unsigned int *)0x7427;	/* Bottom reg. of capture FIFO stack 1*/
volatile unsigned int *CAP2FBOT 	=	(volatile unsigned int *)0x7428;	/* Bottom reg. of capture FIFO stack 2*/
volatile unsigned int *CAP3FBOT 	=	(volatile unsigned int *)0x7429;	/* Bottom reg. of capture FIFO stack 3 */

volatile unsigned int *EVAIMRA 	=	(volatile unsigned int *)0x742C;	/* Group A Interrupt Mask Register */
volatile unsigned int *EVAIMRB 	=	(volatile unsigned int *)0x742D;	/* Group B Interrupt Mask Register */
volatile unsigned int *EVAIMRC 	=	(volatile unsigned int *)0x742E;	/* Group C Interrupt Mask Register */

volatile unsigned int *EVAIFRA 	=	(volatile unsigned int *)0x742F;	/* Group A Interrupt Flag Register*/
volatile unsigned int *EVAIFRB 	=	(volatile unsigned int *)0x7430;	/* Group B Interrupt Flag Register*/
volatile unsigned int *EVAIFRC 	=	(volatile unsigned int *)0x7431;	/* Group C Interrupt Flag Register*/

/* Event Manager B (EVB) registers*/

volatile unsigned int *GPTCONB 	=	(volatile unsigned int *)0x7500;	/* GP Timer control register B */
volatile unsigned int *T3CNT 	=	(volatile unsigned int *)0x7501;	/* GP Timer 3 counter register */
volatile unsigned int *T3CMPR 	=	(volatile unsigned int *)0x7502;	/* GP Timer 3 compare register */
volatile unsigned int *T3PR 	=	(volatile unsigned int *)0x7503;	/* GP Timer 3 period register */
volatile unsigned int *T3CON 	=	(volatile unsigned int *)0x7504;	/* GP Timer 3 control register*/
volatile unsigned int *T4CNT 	=       (volatile unsigned int *)0x7505;	/* GP Timer 4 counter register */
volatile unsigned int *T4CMPR 	=	(volatile unsigned int *)0x7506;	/* GP Timer 4 compare register*/
volatile unsigned int *T4PR 	=       (volatile unsigned int *)0x7507;	/* GP Timer 4 period register*/
volatile unsigned int *T4CON 	=	(volatile unsigned int *)0x7508;	/* GP Timer 4 control register*/

volatile unsigned int *COMCONB 	=	(volatile unsigned int *)0x7511;	/* Compare control register B */
volatile unsigned int *ACTRB 	=	(volatile unsigned int *)0x7513;	/* Full compare Action control register B*/
volatile unsigned int *DBTCONB 	=	(volatile unsigned int *)0x7515;	/* Dead朾and timer control register B*/

volatile unsigned int *CMPR4 	=	(volatile unsigned int *)0x7517;	/* Full compare unit compare register4*/
volatile unsigned int *CMPR5 	=	(volatile unsigned int *)0x7518;	/* Full compare unit compare register5*/
volatile unsigned int *CMPR6 	=	(volatile unsigned int *)0x7519;	/* Full compare unit compare register6*/

volatile unsigned int *CAPCONB 	=	(volatile unsigned int *)0x7520;	/* Capture control register B*/
volatile unsigned int *CAPFIFOB 	=	(volatile unsigned int *)0x7522;	/* Capture FIFO status register B */

volatile unsigned int *CAP4FIFO 	=	(volatile unsigned int *)0x7523;	/* Capture Channel 4 FIFO Top*/
volatile unsigned int *CAP5FIFO 	=	(volatile unsigned int *)0x7524;	/* Capture Channel 5 FIFO Top*/
volatile unsigned int *CAP6FIFO 	=	(volatile unsigned int *)0x7525;	/* Capture Channel 6 FIFO Top */

volatile unsigned int *CAP4FBOT 	=	(volatile unsigned int *)0x7527;	/* Bottom reg. of capture FIFO stack 4 */
volatile unsigned int *CAP5FBOT 	=	(volatile unsigned int *)0x7527;	/* Bottom reg. of capture FIFO stack 5*/
volatile unsigned int *CAP6FBOT 	=	(volatile unsigned int *)0x7527;	/* Bottom reg. of capture FIFO stack 6*/

volatile unsigned int *EVBIMRA 	=	(volatile unsigned int *)0x752C;	/* Group A Interrupt Mask Register */
volatile unsigned int *EVBIMRB 	=	(volatile unsigned int *)0x752D;	/* Group B Interrupt Mask Register */
volatile unsigned int *EVBIMRC 	=	(volatile unsigned int *)0x752E;	/* Group C Interrupt Mask Register */

volatile unsigned int *EVBIFRA 	=	(volatile unsigned int *)0x752F;	/* Group A Interrupt Flag Register*/
volatile unsigned int *EVBIFRB 	=	(volatile unsigned int *)0x7530;	/* Group B Interrupt Flag Register*/
volatile unsigned int *EVBIFRC 	=	(volatile unsigned int *)0x7531;	/* Group C Interrupt Flag Register*/


/*--------------------------------------------------- */
/*I/O space mapped registers  */
/*--------------------------------------------------- */

volatile unsigned int *WSGR 		=	(volatile unsigned int *)0x0FFFF;	
volatile unsigned int *FCMR 		=	(volatile unsigned int *)0x0FF0F;	/* Flash control mode register */

/*--------------------------------------------------- */
/*Bit codes for Test bit instruction (BIT) (15 Loads bit 0 into TC)*/
/*---------------------------------------------------*/
#define BIT15 		  0x0000;	/* Bit Code for 15*/
#define BIT14 		  0x0001;	/* Bit Code for 14*/
#define BIT13 		  0x0002;	/* Bit Code for 13*/
#define BIT12 		  0x0003;	/* Bit Code for 12*/
#define BIT11 		  0x0004;	/* Bit Code for 11*/
#define BIT10 		  0x0005;	/* Bit Code for 10 */
#define BIT9 		  0x0006;	/* Bit Code for 9 */
#define BIT8 		  0x0007;	/* Bit Code for 8 */
#define BIT7 		  0x0008;	/* Bit Code for 7 */
#define BIT6 		  0x0009;	/* Bit Code for 6 */
#define BIT5 		  0x000A;	/* Bit Code for 5*/
#define BIT4 		  0x000B;	/* Bit Code for 4 */
#define BIT3 		  0x000C;	/* Bit Code for 3 */
#define BIT2 		  0x000D;	/* Bit Code for 2*/
#define BIT1 		  0x000E;	/* Bit Code for 1*/
#define BIT0 		  0x000F;	/* Bit Code for 0*/
                                                                   
#define  EINT   asm(" clrc INTM")
#define  DINT   asm(" setc INTM")
#define  ERTM   asm(" clrc DBGM")
#define  DRTM   asm(" setc DBGM")
#define	 EALLOW	asm(" EALLOW")
#define	 EDIS	asm(" EDIS")
#define  ESTOP0 asm(" ESTOP0")