gm2621.chip.gprobe

gm2621的寄存器说明表及调试用到的gprobe

		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8050-ID65.xml]]>
		</long_help>
		<ref id="739"/>
		<ref id="740"/>
		<ref id="741"/>
		<ref id="742"/>
	</register>
	<register size="8" id="66" bit_mask="255" bit_start="0" bit_end="7" address="32849" name="AOC_CTRL1">
		<short_help>
			<![CDATA[Configuration of offset auto adjust timing]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8051-ID66.xml]]>
		</long_help>
		<ref id="743"/>
		<ref id="744"/>
		<ref id="745"/>
	</register>
	<register size="8" id="67" bit_mask="255" bit_start="0" bit_end="7" address="32850" name="AOC_SAMPLE_PER_LINE">
		<short_help>
			<![CDATA[Number of samples of ADC output data read and averaged during the auto adjust sample pulse.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8052-ID67.xml]]>
		</long_help>
		<ref id="746"/>
	</register>
	<register size="8" id="68" bit_mask="255" bit_start="0" bit_end="7" address="32851" name="AOC_Reserved">
		<short_help>
			<![CDATA[AOC reserved register]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8053-ID68.xml]]>
		</long_help>
		<ref id="747"/>
	</register>
	<register size="8" id="69" bit_mask="255" bit_start="0" bit_end="7" address="32852" name="AOC_RESULT_RED_OFFSET1_0">
		<short_help>
			<![CDATA[Offset1 value for the Red channel as calculated by hardware.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8054-ID69.xml]]>
		</long_help>
		<ref id="748"/>
	</register>
	<register size="8" id="70" bit_mask="255" bit_start="0" bit_end="7" address="32853" name="AOC_RESULT_RED_OFFSET1_1">
		<short_help>
			<![CDATA[Offset1 value for the Red channel as calculated by hardware.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8055-ID70.xml]]>
		</long_help>
		<ref id="749"/>
		<ref id="750"/>
	</register>
	<register size="8" id="71" bit_mask="255" bit_start="0" bit_end="7" address="32854" name="AOC_RESULT_GRN_OFFSET1_0">
		<short_help>
			<![CDATA[Offset1 value for the Green channel as calculated by hardware.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8056-ID71.xml]]>
		</long_help>
		<ref id="751"/>
	</register>
	<register size="8" id="72" bit_mask="255" bit_start="0" bit_end="7" address="32855" name="AOC_RESULT_GRN_OFFSET1_1">
		<short_help>
			<![CDATA[Offset1 value for the Green channel as calculated by hardware.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8057-ID72.xml]]>
		</long_help>
		<ref id="752"/>
		<ref id="753"/>
	</register>
	<register size="8" id="73" bit_mask="255" bit_start="0" bit_end="7" address="32856" name="AOC_RESULT_BLU_OFFSET1_0">
		<short_help>
			<![CDATA[Offset1 value for the Blue channel as calculated by hardware.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8058-ID73.xml]]>
		</long_help>
		<ref id="754"/>
	</register>
	<register size="8" id="74" bit_mask="255" bit_start="0" bit_end="7" address="32857" name="AOC_RESULT_BLU_OFFSET1_1">
		<short_help>
			<![CDATA[Offset1 value for the Blue channel as calculated by hardware.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8059-ID74.xml]]>
		</long_help>
		<ref id="755"/>
		<ref id="756"/>
	</register>
	<register size="8" id="75" bit_mask="255" bit_start="0" bit_end="7" address="32858" name="AOC_RESULT_RED_OFFSET2">
		<short_help>
			<![CDATA[Offset2 value for the Red channel as calculated by hardware.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x805A-ID75.xml]]>
		</long_help>
		<ref id="757"/>
		<ref id="758"/>
	</register>
	<register size="8" id="76" bit_mask="255" bit_start="0" bit_end="7" address="32859" name="AOC_RESULT_GRN_OFFSET2">
		<short_help>
			<![CDATA[Offset2 value for the Green channel as calculated by hardware.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x805B-ID76.xml]]>
		</long_help>
		<ref id="759"/>
		<ref id="760"/>
	</register>
	<register size="8" id="77" bit_mask="255" bit_start="0" bit_end="7" address="32860" name="AOC_RESULT_BLU_OFFSET2">
		<short_help>
			<![CDATA[Offset2 value for the Blue channel as calculated by hardware.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x805C-ID77.xml]]>
		</long_help>
		<ref id="761"/>
		<ref id="762"/>
	</register>
	<register size="8" id="78" bit_mask="255" bit_start="0" bit_end="7" address="32862" name="ADC_RED_GRN_OFFSET1_LSB">
		<short_help>
			<![CDATA[Three new LSBs of OFFSET1 for RED and GRN.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x805E-ID78.xml]]>
		</long_help>
		<ref id="763"/>
		<ref id="764"/>
		<ref id="765"/>
		<ref id="766"/>
	</register>
	<register size="8" id="79" bit_mask="255" bit_start="0" bit_end="7" address="32863" name="ADC_BLU_OFFSET1_LSB">
		<short_help>
			<![CDATA[Three new LSBs of OFFSET1 for BLU.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x805F-ID79.xml]]>
		</long_help>
		<ref id="767"/>
		<ref id="768"/>
	</register>
	<register size="8" id="80" bit_mask="255" bit_start="0" bit_end="7" address="32864" name="ADC_CONTROL">
		<short_help>
			<![CDATA[ADC power and input option control]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8060-ID80.xml]]>
		</long_help>
		<ref id="769"/>
		<ref id="770"/>
		<ref id="771"/>
		<ref id="772"/>
		<ref id="773"/>
		<ref id="774"/>
		<ref id="775"/>
	</register>
	<register size="8" id="81" bit_mask="255" bit_start="0" bit_end="7" address="32865" name="ADC_CLAMPSTART">
		<short_help>
			<![CDATA[Programs the start location of ADC clamp signal in increments of SCLKs relative to the trailing edge of HSYNC.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8061-ID81.xml]]>
		</long_help>
		<ref id="776"/>
		<ref id="777"/>
	</register>
	<register size="8" id="82" bit_mask="255" bit_start="0" bit_end="7" address="32866" name="ADC_CLAMPWIDTH">
		<short_help>
			<![CDATA[Programs the width of ADC clamp signal in increments of SCLKs.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8062-ID82.xml]]>
		</long_help>
		<ref id="778"/>
		<ref id="779"/>
	</register>
	<register size="8" id="83" bit_mask="255" bit_start="0" bit_end="7" address="32867" name="ADC_SYNC_LEVEL">
		<short_help>
			<![CDATA[Selection of the input Hsync &amp; Vsync Schmitt-trigger levels]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8063-ID83.xml]]>
		</long_help>
		<ref id="780"/>
		<ref id="781"/>
		<ref id="782"/>
		<ref id="783"/>
	</register>
	<register size="8" id="84" bit_mask="255" bit_start="0" bit_end="7" address="32868" name="ADC_FAS1">
		<short_help>
			<![CDATA[Except for bit D4 (used for ADC internal offset cancellation adjustment), this register is for factory test and evaluation.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8064-ID84.xml]]>
		</long_help>
		<ref id="784"/>
		<ref id="785"/>
		<ref id="786"/>
	</register>
	<register size="8" id="85" bit_mask="255" bit_start="0" bit_end="7" address="32869" name="ADC_FAS2">
		<short_help>
			<![CDATA[This register is for factory test and evaluation.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8065-ID85.xml]]>
		</long_help>
		<ref id="787"/>
	</register>
	<register size="8" id="86" bit_mask="255" bit_start="0" bit_end="7" address="32870" name="ADC_TEST1">
		<short_help>
			<![CDATA[This register is for factory test and evaluation.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8066-ID86.xml]]>
		</long_help>
		<ref id="788"/>
	</register>
	<register size="8" id="87" bit_mask="255" bit_start="0" bit_end="7" address="32871" name="ADC_TEST2">
		<short_help>
			<![CDATA[This register is for factory test and evaluation.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8067-ID87.xml]]>
		</long_help>
		<ref id="789"/>
	</register>
	<register size="8" id="88" bit_mask="255" bit_start="0" bit_end="7" address="32872" name="ADC_DATA_RED">
		<short_help>
			<![CDATA[Register used for testing of the ADC circuitry.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8068-ID88.xml]]>
		</long_help>
		<ref id="790"/>
	</register>
	<register size="8" id="89" bit_mask="255" bit_start="0" bit_end="7" address="32873" name="ADC_DATA_GRN">
		<short_help>
			<![CDATA[Register used for testing of the ADC circuitry.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8069-ID89.xml]]>
		</long_help>
		<ref id="791"/>
	</register>
	<register size="8" id="90" bit_mask="255" bit_start="0" bit_end="7" address="32874" name="ADC_DATA_BLU">
		<short_help>
			<![CDATA[Register used for testing of the ADC circuitry.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x806A-ID90.xml]]>
		</long_help>
		<ref id="792"/>
	</register>
	<register size="8" id="91" bit_mask="255" bit_start="0" bit_end="7" address="32875" name="ADC_FLAGS">
		<short_help>
			<![CDATA[Contains the Overflow and Underflow status flags for the ADC channels.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x806B-ID91.xml]]>
		</long_help>
		<ref id="793"/>
		<ref id="794"/>
		<ref id="795"/>
		<ref id="796"/>
		<ref id="797"/>
		<ref id="798"/>
		<ref id="799"/>
	</register>
	<register size="8" id="92" bit_mask="255" bit_start="0" bit_end="7" address="32876" name="RED_OFFSET1">
		<short_help>
			<![CDATA[Set the DC offset of the T/H first stage for the Red ADC Channel.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x806C-ID92.xml]]>
		</long_help>
		<ref id="800"/>
		<ref id="801"/>
	</register>
	<register size="8" id="93" bit_mask="255" bit_start="0" bit_end="7" address="32877" name="RED_OFFSET2">
		<short_help>
			<![CDATA[Set the DC offset of the T/H second stage for the Red ADC Channel.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x806D-ID93.xml]]>
		</long_help>
		<ref id="802"/>
		<ref id="803"/>
	</register>
	<register size="8" id="94" bit_mask="255" bit_start="0" bit_end="7" address="32878" name="RED_GAIN_0">
		<short_help>
			<![CDATA[Low 8 bits of the 9-bit full scale gain adjustment register for the Red ADC Channel.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x806E-ID94.xml]]>
		</long_help>
		<ref id="804"/>
	</register>
	<register size="8" id="95" bit_mask="255" bit_start="0" bit_end="7" address="32879" name="RED_GAIN_1">
		<short_help>
			<![CDATA[Bit D8 (MSB) of the 9-bit full scale gain adjustment register for the Red ADC Channel.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x806F-ID95.xml]]>
		</long_help>
		<ref id="805"/>
		<ref id="806"/>
	</register>
	<register size="8" id="96" bit_mask="255" bit_start="0" bit_end="7" address="32880" name="GRN_OFFSET1">
		<short_help>
			<![CDATA[Set the DC offset of the T/H first stage for the Green ADC Channel.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8070-ID96.xml]]>
		</long_help>
		<ref id="807"/>
		<ref id="808"/>
	</register>
	<register size="8" id="97" bit_mask="255" bit_start="0" bit_end="7" address="32881" name="GRN_OFFSET2">
		<short_help>
			<![CDATA[Set the DC offset of the T/H second stage for the Green ADC Channel.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8071-ID97.xml]]>
		</long_help>
		<ref id="809"/>
		<ref id="810"/>
	</register>
	<register size="8" id="98" bit_mask="255" bit_start="0" bit_end="7" address="32882" name="GRN_GAIN_0">
		<short_help>
			<![CDATA[Low 8 bits of the 9-bit full scale gain adjustment register for the Green ADC C3hannel.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8072-ID98.xml]]>
		</long_help>
		<ref id="811"/>
	</register>
	<register size="8" id="99" bit_mask="255" bit_start="0" bit_end="7" address="32883" name="GRN_GAIN_1">
		<short_help>
			<![CDATA[Bit D8 (MSB) of the 9-bit full scale gain adjustment register for the Green ADC Channel.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8073-ID99.xml]]>
		</long_help>
		<ref id="812"/>
		<ref id="813"/>
	</register>
	<register size="8" id="100" bit_mask="255" bit_start="0" bit_end="7" address="32884" name="BLU_OFFSET1">
		<short_help>
			<![CDATA[Set the DC offset of the T/H first stage for the Blue ADC Channel.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8074-ID100.xml]]>
		</long_help>
		<ref id="814"/>
		<ref id="815"/>
	</register>
	<register size="8" id="101" bit_mask="255" bit_start="0" bit_end="7" address="32885" name="BLU_OFFSET2">
		<short_help>
			<![CDATA[Set the DC offset T/H second stage for the Blue ADC Channel.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8075-ID101.xml]]>
		</long_help>
		<ref id="816"/>
		<ref id="817"/>
	</register>
	<register size="8" id="102" bit_mask="255" bit_start="0" bit_end="7" address="32886" name="BLU_GAIN_0">
		<short_help>
			<![CDATA[Low 8 bits of the 9-bit full scale gain adjustment register for the Blue ADC Channel.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8076-ID102.xml]]>
		</long_help>
		<ref id="818"/>
	</register>
	<register size="8" id="103" bit_mask="255" bit_start="0" bit_end="7" address="32887" name="BLU_GAIN_1">
		<short_help>
			<![CDATA[Bit D8 (MSB) of the 9-bit full scale gain adjustment register for the Blue ADC Channel.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8077-ID103.xml]]>
		</long_help>
		<ref id="819"/>
		<ref id="820"/>
	</register>
	<register size="8" id="104" bit_mask="255" bit_start="0" bit_end="7" address="32888" name="ADC_TESTDAC">
		<short_help>
			<![CDATA[Bits D2:0 enable an internal DAC for ADC self-calibration.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8078-ID104.xml]]>
		</long_help>
		<ref id="821"/>
		<ref id="822"/>
		<ref id="823"/>
		<ref id="824"/>
		<ref id="825"/>
	</register>
	<register size="8" id="105" bit_mask="255" bit_start="0" bit_end="7" address="32889" name="ADC_DAC_DATA">
		<short_help>
			<![CDATA[The output of DAC can be applied internally to the RGB inputs depending on the state of 0x8078[2:0]]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8079-ID105.xml]]>
		</long_help>
		<ref id="826"/>
	</register>
	<register size="8" id="106" bit_mask="255" bit_start="0" bit_end="7" address="32890" name="ADC_MODULATION">
		<short_help>
			<![CDATA[Except for bit 6, this register is for factory test and evaluation.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x807A-ID106.xml]]>
		</long_help>