gm2621.chip.gprobe

gm2621的寄存器说明表及调试用到的gprobe

		</long_help>
		<ref id="590"/>
		<ref id="591"/>
		<ref id="592"/>
		<ref id="593"/>
		<ref id="594"/>
		<ref id="595"/>
	</register>
	<register size="8" id="32" bit_mask="255" bit_start="0" bit_end="7" address="32810" name="SPI_CONTROL">
		<short_help>
			<![CDATA[This register controls the SPI clock.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x802A-ID32.xml]]>
		</long_help>
		<ref id="596"/>
		<ref id="597"/>
		<ref id="598"/>
		<ref id="599"/>
		<ref id="600"/>
		<ref id="601"/>
	</register>
	<register size="8" id="33" bit_mask="255" bit_start="0" bit_end="7" address="32811" name="SPI_STATUS">
		<short_help>
			<![CDATA[This register sets the status of SPI, and has an error flag for data exchange operation.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x802B-ID33.xml]]>
		</long_help>
		<ref id="602"/>
		<ref id="603"/>
		<ref id="604"/>
		<ref id="605"/>
		<ref id="606"/>
	</register>
	<register size="8" id="34" bit_mask="255" bit_start="0" bit_end="7" address="32812" name="SPI_DATA_0">
		<short_help>
			<![CDATA[This is really a RW register.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x802C-ID34.xml]]>
		</long_help>
		<ref id="607"/>
	</register>
	<register size="8" id="35" bit_mask="255" bit_start="0" bit_end="7" address="32813" name="SPI_DATA_1">
		<short_help>
			<![CDATA[This is really a RW register.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x802D-ID35.xml]]>
		</long_help>
		<ref id="608"/>
	</register>
	<register size="8" id="36" bit_mask="255" bit_start="0" bit_end="7" address="32814" name="SPI_CACHE_CTRL">
		<short_help>
			<![CDATA[This register sets cache controller operation with OCM read of SPI data.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x802E-ID36.xml]]>
		</long_help>
		<ref id="609"/>
		<ref id="610"/>
		<ref id="611"/>
	</register>
	<register size="8" id="37" bit_mask="255" bit_start="0" bit_end="7" address="32816" name="PWM0_CONFIG">
		<short_help>
			<![CDATA[The PWM0 functional configuration.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8030-ID37.xml]]>
		</long_help>
		<ref id="612"/>
		<ref id="613"/>
		<ref id="614"/>
		<ref id="615"/>
		<ref id="616"/>
		<ref id="617"/>
		<ref id="618"/>
	</register>
	<register size="8" id="38" bit_mask="255" bit_start="0" bit_end="7" address="32817" name="PWM0_PERIOD">
		<short_help>
			<![CDATA[PWM0_PULSE will generate a PWM0 period based on of PWM clock source pulses.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8031-ID38.xml]]>
		</long_help>
		<ref id="619"/>
	</register>
	<register size="8" id="39" bit_mask="255" bit_start="0" bit_end="7" address="32818" name="PWM0_PULSE">
		<short_help>
			<![CDATA[PWM0_PULSE will generate a PWM0 pulse duty cycle based on of PWM clock source pulses.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8032-ID39.xml]]>
		</long_help>
		<ref id="620"/>
	</register>
	<register size="8" id="40" bit_mask="255" bit_start="0" bit_end="7" address="32819" name="PWM1_CONFIG">
		<short_help>
			<![CDATA[The PWM1 functional configuration.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8033-ID40.xml]]>
		</long_help>
		<ref id="621"/>
		<ref id="622"/>
		<ref id="623"/>
		<ref id="624"/>
		<ref id="625"/>
		<ref id="626"/>
		<ref id="627"/>
	</register>
	<register size="8" id="41" bit_mask="255" bit_start="0" bit_end="7" address="32820" name="PWM1_PERIOD">
		<short_help>
			<![CDATA[PWM1_PULSE will generate a PWM1 period based on of PWM clock source pulses.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8034-ID41.xml]]>
		</long_help>
		<ref id="628"/>
	</register>
	<register size="8" id="42" bit_mask="255" bit_start="0" bit_end="7" address="32821" name="PWM1_PULSE">
		<short_help>
			<![CDATA[PWM1_PULSE will generate a PWM1 pulse duty cycle based on of PWM clock source pulses.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8035-ID42.xml]]>
		</long_help>
		<ref id="629"/>
	</register>
	<register size="8" id="43" bit_mask="255" bit_start="0" bit_end="7" address="32822" name="PWM2_CONFIG">
		<short_help>
			<![CDATA[The PWM2 functional configuration.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8036-ID43.xml]]>
		</long_help>
		<ref id="630"/>
		<ref id="631"/>
		<ref id="632"/>
		<ref id="633"/>
		<ref id="634"/>
		<ref id="635"/>
		<ref id="636"/>
	</register>
	<register size="8" id="44" bit_mask="255" bit_start="0" bit_end="7" address="32823" name="PWM2_PERIOD">
		<short_help>
			<![CDATA[PWM2_PULSE will generate a PWM2 period based on of PWM clock source pulses.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8037-ID44.xml]]>
		</long_help>
		<ref id="637"/>
	</register>
	<register size="8" id="45" bit_mask="255" bit_start="0" bit_end="7" address="32824" name="PWM2_PULSE">
		<short_help>
			<![CDATA[PWM2_PULSE will generate a PWM2 pulse duty cycle based on of PWM clock source pulses.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8038-ID45.xml]]>
		</long_help>
		<ref id="638"/>
	</register>
	<register size="8" id="46" bit_mask="255" bit_start="0" bit_end="7" address="32825" name="PWM3_CONFIG">
		<short_help>
			<![CDATA[The PWM3 functional configuration.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8039-ID46.xml]]>
		</long_help>
		<ref id="639"/>
		<ref id="640"/>
		<ref id="641"/>
		<ref id="642"/>
		<ref id="643"/>
		<ref id="644"/>
		<ref id="645"/>
	</register>
	<register size="8" id="47" bit_mask="255" bit_start="0" bit_end="7" address="32826" name="PWM3_PERIOD">
		<short_help>
			<![CDATA[PWM3_PULSE will generate a PWM3 period based on of PWM clock source pulses.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x803A-ID47.xml]]>
		</long_help>
		<ref id="646"/>
	</register>
	<register size="8" id="48" bit_mask="255" bit_start="0" bit_end="7" address="32827" name="PWM3_PULSE">
		<short_help>
			<![CDATA[PWM3_PULSE will generate a PWM3 pulse duty cycle based on of PWM clock source pulses.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x803B-ID48.xml]]>
		</long_help>
		<ref id="647"/>
	</register>
	<register size="8" id="49" bit_mask="255" bit_start="0" bit_end="7" address="32828" name="GPIO_DIRCTRL1">
		<short_help>
			<![CDATA[Sets the input/output direction of GPIO[14:8]]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x803C-ID49.xml]]>
		</long_help>
		<ref id="648"/>
		<ref id="649"/>
		<ref id="650"/>
		<ref id="651"/>
		<ref id="652"/>
		<ref id="653"/>
		<ref id="654"/>
		<ref id="655"/>
	</register>
	<register size="8" id="50" bit_mask="255" bit_start="0" bit_end="7" address="32829" name="GPO_OPENDRAIN_EN1">
		<short_help>
			<![CDATA[Selects open drain or active drive for GPIO[14:8]]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x803D-ID50.xml]]>
		</long_help>
		<ref id="656"/>
		<ref id="657"/>
		<ref id="658"/>
		<ref id="659"/>
		<ref id="660"/>
		<ref id="661"/>
		<ref id="662"/>
		<ref id="663"/>
	</register>
	<register size="8" id="51" bit_mask="255" bit_start="0" bit_end="7" address="32830" name="GPINPUT1">
		<short_help>
			<![CDATA[Reads the value currently available on external pins GPIO[14:8]]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x803E-ID51.xml]]>
		</long_help>
		<ref id="664"/>
		<ref id="665"/>
		<ref id="666"/>
		<ref id="667"/>
		<ref id="668"/>
		<ref id="669"/>
		<ref id="670"/>
		<ref id="671"/>
	</register>
	<register size="8" id="52" bit_mask="255" bit_start="0" bit_end="7" address="32831" name="GPOUTPUT1">
		<short_help>
			<![CDATA[Output value for output configured pins GPIO[14:8]]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x803F-ID52.xml]]>
		</long_help>
		<ref id="672"/>
		<ref id="673"/>
		<ref id="674"/>
		<ref id="675"/>
		<ref id="676"/>
		<ref id="677"/>
		<ref id="678"/>
		<ref id="679"/>
	</register>
	<register size="8" id="53" bit_mask="255" bit_start="0" bit_end="7" address="32832" name="GPO_OUTPUT">
		<short_help>
			<![CDATA[Sets the output levels for the GPO pins]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8040-ID53.xml]]>
		</long_help>
		<ref id="680"/>
		<ref id="681"/>
		<ref id="682"/>
		<ref id="683"/>
		<ref id="684"/>
		<ref id="685"/>
		<ref id="686"/>
	</register>
	<register size="8" id="54" bit_mask="255" bit_start="0" bit_end="7" address="32833" name="GPO_OPENDRAIN_EN">
		<short_help>
			<![CDATA[Selects open drain or active drive for the GPO pins]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8041-ID54.xml]]>
		</long_help>
		<ref id="687"/>
		<ref id="688"/>
		<ref id="689"/>
		<ref id="690"/>
		<ref id="691"/>
		<ref id="692"/>
	</register>
	<register size="8" id="55" bit_mask="255" bit_start="0" bit_end="7" address="32834" name="GPINPUT">
		<short_help>
			<![CDATA[Reads back the level on GPO_2 pin.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8042-ID55.xml]]>
		</long_help>
		<ref id="693"/>
		<ref id="694"/>
		<ref id="695"/>
	</register>
	<register size="8" id="56" bit_mask="255" bit_start="0" bit_end="7" address="32836" name="GPIO_DIRCTRL2">
		<short_help>
			<![CDATA[Sets the input/output direction and control of shared GPIO[19:16] on DDC pins]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8044-ID56.xml]]>
		</long_help>
		<ref id="696"/>
		<ref id="697"/>
		<ref id="698"/>
		<ref id="699"/>
		<ref id="700"/>
		<ref id="701"/>
		<ref id="702"/>
		<ref id="703"/>
	</register>
	<register size="8" id="57" bit_mask="255" bit_start="0" bit_end="7" address="32837" name="GPO_OPENDRAIN_EN2">
		<short_help>
			<![CDATA[Selects open drain or active drive for GPIO[19:16]]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8045-ID57.xml]]>
		</long_help>
		<ref id="704"/>
		<ref id="705"/>
		<ref id="706"/>
		<ref id="707"/>
		<ref id="708"/>
	</register>
	<register size="8" id="58" bit_mask="255" bit_start="0" bit_end="7" address="32838" name="GPINPUT2">
		<short_help>
			<![CDATA[Reads the value currently available on external pins GPIO[19:16] shared on DDC pins]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8046-ID58.xml]]>
		</long_help>
		<ref id="709"/>
		<ref id="710"/>
		<ref id="711"/>
		<ref id="712"/>
		<ref id="713"/>
	</register>
	<register size="8" id="59" bit_mask="255" bit_start="0" bit_end="7" address="32839" name="GPOUTPUT2">
		<short_help>
			<![CDATA[Output value for output configured pins GPIO[19:16] shared with DDC pins, LBADC and VBUFC]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8047-ID59.xml]]>
		</long_help>
		<ref id="714"/>
		<ref id="715"/>
		<ref id="716"/>
		<ref id="717"/>
		<ref id="718"/>
		<ref id="719"/>
		<ref id="720"/>
		<ref id="721"/>
	</register>
	<register size="8" id="60" bit_mask="255" bit_start="0" bit_end="7" address="32840" name="LOW_BW_ADC_CTRL">
		<short_help>
			<![CDATA[Low Bandwidth ADC Controller.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8048-ID60.xml]]>
		</long_help>
		<ref id="722"/>
		<ref id="723"/>
		<ref id="724"/>
		<ref id="725"/>
		<ref id="726"/>
		<ref id="727"/>
	</register>
	<register size="8" id="61" bit_mask="255" bit_start="0" bit_end="7" address="32841" name="LOW_BW_ADC_RESULT">
		<short_help>
			<![CDATA[This register shows the data result from adc conversion of the selected input signal.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8049-ID61.xml]]>
		</long_help>
		<ref id="728"/>
	</register>
	<register size="8" id="62" bit_mask="255" bit_start="0" bit_end="7" address="32842" name="LOW_BW_ADC_STATUS">
		<short_help>
			<![CDATA[This registers shows the status of adc conversion of the selected input signal.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x804A-ID62.xml]]>
		</long_help>
		<ref id="729"/>
		<ref id="730"/>
	</register>
	<register size="8" id="63" bit_mask="255" bit_start="0" bit_end="7" address="32844" name="LBADC_OUT_EN">
		<short_help>
			<![CDATA[To enable LBADC 3 channels as GPOs.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x804C-ID63.xml]]>
		</long_help>
		<ref id="731"/>
		<ref id="732"/>
		<ref id="733"/>
		<ref id="734"/>
		<ref id="735"/>
	</register>
	<register size="8" id="64" bit_mask="255" bit_start="0" bit_end="7" address="32845" name="POWER_STATUS">
		<short_help>
			<![CDATA[This register is to select the reference voltage level POR to monitor and status of Power monitoring.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x804D-ID64.xml]]>
		</long_help>
		<ref id="736"/>
		<ref id="737"/>
		<ref id="738"/>
	</register>
	<register size="8" id="65" bit_mask="255" bit_start="0" bit_end="7" address="32848" name="AOC_CTRL0">
		<short_help>
			<![CDATA[Enable and configuration for the ADC auto adjustment of Offset]]>
		</short_help>