gm2621.chip.gprobe

gm2621的寄存器说明表及调试用到的gprobe

		<ref id="418"/>
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		<ref id="463"/>
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		<ref id="465"/>
		<ref id="466"/>
		<ref id="467"/>
	</category>
	<register size="8" id="1" bit_mask="255" bit_start="0" bit_end="7" address="32768" name="HOST_CONTROL">
		<short_help>
			<![CDATA[Control updating of all PA-type registers.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8000-ID1.xml]]>
		</long_help>
		<ref id="468"/>
		<ref id="469"/>
		<ref id="470"/>
		<ref id="471"/>
		<ref id="472"/>
		<ref id="473"/>
	</register>
	<register size="8" id="2" bit_mask="255" bit_start="0" bit_end="7" address="32769" name="PRODUCT_ID">
		<short_help>
			<![CDATA[This register indicates gm26xx chip ID.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8001-ID2.xml]]>
		</long_help>
		<ref id="474"/>
	</register>
	<register size="8" id="3" bit_mask="255" bit_start="0" bit_end="7" address="32770" name="PRODUCT_REV">
		<short_help>
			<![CDATA[This register shows the gm5xxx PRODUCT_REV number.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8002-ID3.xml]]>
		</long_help>
		<ref id="475"/>
	</register>
	<register size="8" id="4" bit_mask="255" bit_start="0" bit_end="7" address="32771" name="CLOCK_CONFIG">
		<short_help>
			<![CDATA[This register selects the clock source for IFM, IP, OCM and DP clock domains.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8003-ID4.xml]]>
		</long_help>
		<ref id="476"/>
		<ref id="477"/>
		<ref id="478"/>
		<ref id="479"/>
		<ref id="480"/>
	</register>
	<register size="8" id="5" bit_mask="255" bit_start="0" bit_end="7" address="32772" name="OCM_TCLK_DIV">
		<short_help>
			<![CDATA[Divides the TCLK by register value * 2 to provide a very low frequency OCM clock for low power sleep mode.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8004-ID5.xml]]>
		</long_help>
		<ref id="481"/>
	</register>
	<register size="8" id="6" bit_mask="255" bit_start="0" bit_end="7" address="32774" name="BYPASS">
		<short_help>
			<![CDATA[Clock power-down and Scaler Bypass Control]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8006-ID6.xml]]>
		</long_help>
		<ref id="482"/>
		<ref id="483"/>
		<ref id="484"/>
		<ref id="485"/>
		<ref id="486"/>
		<ref id="487"/>
		<ref id="488"/>
	</register>
	<register size="8" id="7" bit_mask="255" bit_start="0" bit_end="7" address="32779" name="IRQ_CONFIG">
		<short_help>
			<![CDATA[Configures the operation of Interrupt output pin.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x800B-ID7.xml]]>
		</long_help>
		<ref id="489"/>
		<ref id="490"/>
		<ref id="491"/>
		<ref id="492"/>
	</register>
	<register size="8" id="8" bit_mask="255" bit_start="0" bit_end="7" address="32780" name="IFM_OCMMASK">
		<short_help>
			<![CDATA[This is the OCM IRQ3 mask register.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x800C-ID8.xml]]>
		</long_help>
		<ref id="493"/>
		<ref id="494"/>
		<ref id="495"/>
		<ref id="496"/>
		<ref id="497"/>
		<ref id="498"/>
		<ref id="499"/>
		<ref id="500"/>
	</register>
	<register size="8" id="9" bit_mask="255" bit_start="0" bit_end="7" address="32781" name="INPUT_OCMMASK">
		<short_help>
			<![CDATA[This is the OCM IRQ4 mask register.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x800D-ID9.xml]]>
		</long_help>
		<ref id="501"/>
		<ref id="502"/>
		<ref id="503"/>
		<ref id="504"/>
		<ref id="505"/>
		<ref id="506"/>
		<ref id="507"/>
		<ref id="508"/>
	</register>
	<register size="8" id="10" bit_mask="255" bit_start="0" bit_end="7" address="32782" name="MISC_OCMMASK">
		<short_help>
			<![CDATA[This is the OCM IRQ5 mask register.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x800E-ID10.xml]]>
		</long_help>
		<ref id="509"/>
		<ref id="510"/>
		<ref id="511"/>
		<ref id="512"/>
		<ref id="513"/>
		<ref id="514"/>
		<ref id="515"/>
		<ref id="516"/>
	</register>
	<register size="8" id="11" bit_mask="255" bit_start="0" bit_end="7" address="32783" name="SYSTEM_STATUS">
		<short_help>
			<![CDATA[External Micro-controller interrupt summary.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x800F-ID11.xml]]>
		</long_help>
		<ref id="517"/>
		<ref id="518"/>
		<ref id="519"/>
		<ref id="520"/>
		<ref id="521"/>
		<ref id="522"/>
		<ref id="523"/>
	</register>
	<register size="8" id="12" bit_mask="255" bit_start="0" bit_end="7" address="32784" name="IFM_STATUS">
		<short_help>
			<![CDATA[This register indicates the status of IFM timing change flags.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8010-ID12.xml]]>
		</long_help>
		<ref id="524"/>
		<ref id="525"/>
		<ref id="526"/>
		<ref id="527"/>
		<ref id="528"/>
		<ref id="529"/>
		<ref id="530"/>
		<ref id="531"/>
	</register>
	<register size="8" id="13" bit_mask="255" bit_start="0" bit_end="7" address="32785" name="INPUT_STATUS">
		<short_help>
			<![CDATA[Status flags for input timing events.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8011-ID13.xml]]>
		</long_help>
		<ref id="532"/>
		<ref id="533"/>
		<ref id="534"/>
		<ref id="535"/>
		<ref id="536"/>
		<ref id="537"/>
		<ref id="538"/>
		<ref id="539"/>
	</register>
	<register size="8" id="14" bit_mask="255" bit_start="0" bit_end="7" address="32786" name="DISPLAY_STATUS">
		<short_help>
			<![CDATA[Status flags for Display timing events.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8012-ID14.xml]]>
		</long_help>
		<ref id="540"/>
		<ref id="541"/>
		<ref id="542"/>
		<ref id="543"/>
		<ref id="544"/>
		<ref id="545"/>
		<ref id="546"/>
		<ref id="547"/>
	</register>
	<register size="8" id="15" bit_mask="255" bit_start="0" bit_end="7" address="32787" name="CLOCK_STATUS">
		<short_help>
			<![CDATA[Status flags for clock events.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8013-ID15.xml]]>
		</long_help>
		<ref id="548"/>
		<ref id="549"/>
		<ref id="550"/>
		<ref id="551"/>
		<ref id="552"/>
		<ref id="553"/>
	</register>
	<register size="8" id="16" bit_mask="255" bit_start="0" bit_end="7" address="32788" name="MISC_STATUS">
		<short_help>
			<![CDATA[Various real-time status bits, Input Vsync, Input Active, ADC calibration]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8014-ID16.xml]]>
		</long_help>
		<ref id="554"/>
		<ref id="555"/>
		<ref id="556"/>
		<ref id="557"/>
	</register>
	<register size="8" id="17" bit_mask="255" bit_start="0" bit_end="7" address="32790" name="RCLK_CONFIG">
		<short_help>
			<![CDATA[Power control for RCLK PLL.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8016-ID17.xml]]>
		</long_help>
		<ref id="558"/>
		<ref id="559"/>
		<ref id="560"/>
		<ref id="561"/>
	</register>
	<register size="8" id="18" bit_mask="255" bit_start="0" bit_end="7" address="32791" name="RCLK_FREQUENCY">
		<short_help>
			<![CDATA[Sets the RCLK pll frequency.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8017-ID18.xml]]>
		</long_help>
		<ref id="562"/>
		<ref id="563"/>
		<ref id="564"/>
	</register>
	<register size="8" id="19" bit_mask="255" bit_start="0" bit_end="7" address="32792" name="RCLK_PLL">
		<short_help>
			<![CDATA[RCLK pll and TCLK oscillator adjustments.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8018-ID19.xml]]>
		</long_help>
		<ref id="565"/>
		<ref id="566"/>
		<ref id="567"/>
		<ref id="568"/>
		<ref id="569"/>
		<ref id="570"/>
		<ref id="571"/>
		<ref id="572"/>
	</register>
	<register size="8" id="20" bit_mask="255" bit_start="0" bit_end="7" address="32794" name="FCLK_FREQ_0">
		<short_help>
			<![CDATA[This register sets the operating frequency of FCLK, this fixed frequency clock is used to drive the OCM.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x801A-ID20.xml]]>
		</long_help>
		<ref id="573"/>
	</register>
	<register size="8" id="21" bit_mask="255" bit_start="0" bit_end="7" address="32795" name="FCLK_FREQ_1">
		<short_help>
			<![CDATA[This register sets the operating frequency of FCLK, this fixed frequency clock is used to drive the OCM.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x801B-ID21.xml]]>
		</long_help>
		<ref id="574"/>
	</register>
	<register size="8" id="22" bit_mask="255" bit_start="0" bit_end="7" address="32796" name="LCLK_FREQ_0">
		<short_help>
			<![CDATA[This register sets the operating frequency of LCLK, this fixed frequency clock is used to drive Expander Line Buffer.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x801C-ID22.xml]]>
		</long_help>
		<ref id="575"/>
	</register>
	<register size="8" id="23" bit_mask="255" bit_start="0" bit_end="7" address="32797" name="LCLK_FREQ_1">
		<short_help>
			<![CDATA[This register sets the operating frequency of LCLK, this fixed frequency clock is used to drive Expander Line Buffer.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x801D-ID23.xml]]>
		</long_help>
		<ref id="576"/>
	</register>
	<register size="8" id="24" bit_mask="255" bit_start="0" bit_end="7" address="32800" name="OCM_BUS_CONTROL">
		<short_help>
			<![CDATA[This register controls OCM BUS WDT.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8020-ID24.xml]]>
		</long_help>
		<ref id="577"/>
		<ref id="578"/>
		<ref id="579"/>
		<ref id="580"/>
	</register>
	<register size="8" id="25" bit_mask="255" bit_start="0" bit_end="7" address="32801" name="OCM_WBUF_STATUS">
		<short_help>
			<![CDATA[This register sets the status for OCM sram Write Buffers.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8021-ID25.xml]]>
		</long_help>
		<ref id="581"/>
		<ref id="582"/>
	</register>
	<register size="8" id="26" bit_mask="255" bit_start="0" bit_end="7" address="32802" name="OCM_BUS_WDT_INIT">
		<short_help>
			<![CDATA[This register sets init value of OCM BUS WDT countdown timer, which determines transaction allowed time in MCU clock cycles.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8022-ID26.xml]]>
		</long_help>
		<ref id="583"/>
	</register>
	<register size="8" id="27" bit_mask="255" bit_start="0" bit_end="7" address="32803" name="OCM_BUS_WDT_STATUS">
		<short_help>
			<![CDATA[This register is used to slow device memory that failed to complete within timeout.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8023-ID27.xml]]>
		</long_help>
		<ref id="584"/>
		<ref id="585"/>
	</register>
	<register size="8" id="28" bit_mask="255" bit_start="0" bit_end="7" address="32804" name="OCM_WDT_ERR_ADDR_0">
		<short_help>
			<![CDATA[This register shows transaction errors.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8024-ID28.xml]]>
		</long_help>
		<ref id="586"/>
	</register>
	<register size="8" id="29" bit_mask="255" bit_start="0" bit_end="7" address="32805" name="OCM_WDT_ERR_ADDR_1">
		<short_help>
			<![CDATA[This register shows transaction errors.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8025-ID29.xml]]>
		</long_help>
		<ref id="587"/>
	</register>
	<register size="8" id="30" bit_mask="255" bit_start="0" bit_end="7" address="32806" name="OCM_WDT_ERR_ADDR_2">
		<short_help>
			<![CDATA[This register shows transaction errors.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8026-ID30.xml]]>
		</long_help>
		<ref id="588"/>
		<ref id="589"/>
	</register>
	<register size="8" id="31" bit_mask="255" bit_start="0" bit_end="7" address="32807" name="OCM_CONTROL">
		<short_help>
			<![CDATA[This register controls the OCM.]]>
		</short_help>
		<long_help>
			<![CDATA[ms-its:%PATH%gm2621.chm::/0x8027-ID31.xml]]>