ccd.tan.rpt

本程序通过CPLD不同的波形来控制CCD的驱动

+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Web Edition
    Info: Processing started: Tue Apr 21 15:05:53 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off CCD -c CCD
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "LessThan1~38" as buffer
    Info: Detected ripple clock "clk_tempr" as buffer
    Info: Detected ripple clock "cnt3[2]" as buffer
    Info: Detected ripple clock "cnt3[1]" as buffer
Info: Clock "clk" has Internal fmax of 140.85 MHz between source register "cnt[0]" and destination register "cnt[0]" (period= 7.1 ns)
    Info: + Longest register to register delay is 4.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC18; Fanout = 3; REG Node = 'cnt[0]'
        Info: 2: + IC(1.300 ns) + CELL(3.200 ns) = 4.500 ns; Loc. = LC18; Fanout = 3; REG Node = 'cnt[0]'
        Info: Total cell delay = 3.200 ns ( 71.11 % )
        Info: Total interconnect delay = 1.300 ns ( 28.89 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.100 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.100 ns; Loc. = LC18; Fanout = 3; REG Node = 'cnt[0]'
            Info: Total cell delay = 2.100 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 2.100 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.100 ns; Loc. = LC18; Fanout = 3; REG Node = 'cnt[0]'
            Info: Total cell delay = 2.100 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Micro setup delay of destination is 1.000 ns
Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "clk_tempr" and destination pin or register "clk_tempc" for clock "clk" (Hold time is 5.9 ns)
    Info: + Largest clock skew is 10.000 ns
        Info: + Longest clock path from clock "clk" to destination register is 12.100 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(2.200 ns) = 3.700 ns; Loc. = LC9; Fanout = 9; REG Node = 'cnt3[1]'
            Info: 3: + IC(1.300 ns) + CELL(3.800 ns) = 8.800 ns; Loc. = SEXP2; Fanout = 1; COMB Node = 'LessThan1~38'
            Info: 4: + IC(0.000 ns) + CELL(3.300 ns) = 12.100 ns; Loc. = LC1; Fanout = 3; REG Node = 'clk_tempc'
            Info: Total cell delay = 10.800 ns ( 89.26 % )
            Info: Total interconnect delay = 1.300 ns ( 10.74 % )
        Info: - Shortest clock path from clock "clk" to source register is 2.100 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.100 ns; Loc. = LC17; Fanout = 4; REG Node = 'clk_tempr'
            Info: Total cell delay = 2.100 ns ( 100.00 % )
    Info: - Micro clock to output delay of source is 1.600 ns
    Info: - Shortest register to register delay is 4.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC17; Fanout = 4; REG Node = 'clk_tempr'
        Info: 2: + IC(1.300 ns) + CELL(3.200 ns) = 4.500 ns; Loc. = LC1; Fanout = 3; REG Node = 'clk_tempc'
        Info: Total cell delay = 3.200 ns ( 71.11 % )
        Info: Total interconnect delay = 1.300 ns ( 28.89 % )
    Info: + Micro hold delay of destination is 2.000 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Info: tsu for register "cnt[0]" (data pin = "start", clock pin = "clk") is 3.700 ns
    Info: + Longest pin to register delay is 4.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_81; Fanout = 12; PIN Node = 'start'
        Info: 2: + IC(1.400 ns) + CELL(3.200 ns) = 4.800 ns; Loc. = LC18; Fanout = 3; REG Node = 'cnt[0]'
        Info: Total cell delay = 3.400 ns ( 70.83 % )
        Info: Total interconnect delay = 1.400 ns ( 29.17 % )
    Info: + Micro setup delay of destination is 1.000 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.100 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.100 ns; Loc. = LC18; Fanout = 3; REG Node = 'cnt[0]'
        Info: Total cell delay = 2.100 ns ( 100.00 % )
Info: tco from clock "clk" to destination pin "CLAMP2" through register "clk_tempc" is 19.500 ns
    Info: + Longest clock path from clock "clk" to source register is 12.100 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(2.200 ns) = 3.700 ns; Loc. = LC9; Fanout = 9; REG Node = 'cnt3[1]'
        Info: 3: + IC(1.300 ns) + CELL(3.800 ns) = 8.800 ns; Loc. = SEXP2; Fanout = 1; COMB Node = 'LessThan1~38'
        Info: 4: + IC(0.000 ns) + CELL(3.300 ns) = 12.100 ns; Loc. = LC1; Fanout = 3; REG Node = 'clk_tempc'
        Info: Total cell delay = 10.800 ns ( 89.26 % )
        Info: Total interconnect delay = 1.300 ns ( 10.74 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Longest register to pin delay is 5.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 3; REG Node = 'clk_tempc'
        Info: 2: + IC(1.300 ns) + CELL(4.200 ns) = 5.500 ns; Loc. = LC3; Fanout = 1; COMB Node = 'CLAMP2~9'
        Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 5.800 ns; Loc. = PIN_20; Fanout = 0; PIN Node = 'CLAMP2'
        Info: Total cell delay = 4.500 ns ( 77.59 % )
        Info: Total interconnect delay = 1.300 ns ( 22.41 % )
Info: th for register "cnt[0]" (data pin = "start", clock pin = "clk") is -0.700 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.100 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.100 ns; Loc. = LC18; Fanout = 3; REG Node = 'cnt[0]'
        Info: Total cell delay = 2.100 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 2.000 ns
    Info: - Shortest pin to register delay is 4.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_81; Fanout = 12; PIN Node = 'start'
        Info: 2: + IC(1.400 ns) + CELL(3.200 ns) = 4.800 ns; Loc. = LC18; Fanout = 3; REG Node = 'cnt[0]'
        Info: Total cell delay = 3.400 ns ( 70.83 % )
        Info: Total interconnect delay = 1.400 ns ( 29.17 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings
    Info: Peak virtual memory: 120 megabytes
    Info: Processing ended: Tue Apr 21 15:05:54 2009
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01