ccd.fnsim.qmsg

本程序通过CPLD不同的波形来控制CCD的驱动

{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\|addcore:adder\[0\]\|a_csnbuffer:oflow_node lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\|addcore:adder\[0\]\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "e:/quartes/quartus/libraries/megafunctions/addcore.tdf" 97 2 0 } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 43 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|addcore:adder\|addcore:adder\[0\]\|a_csnbuffer:result_node lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|addcore:adder\|addcore:adder\[0\]\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "e:/quartes/quartus/libraries/megafunctions/addcore.tdf" 189 5 0 } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 43 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:result_ext_latency_ffs lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "e:/quartes/quartus/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 43 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add0\|altshift:carry_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "e:/quartes/quartus/libraries/megafunctions/lpm_add_sub.tdf" 288 2 0 } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 43 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add1\"" {  } { { "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add1 " "Info: Instantiated megafunction \"lpm_add_sub:Add1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 2 " "Info: Parameter \"LPM_WIDTH\" = \"2\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add1\|addcore:adder lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add1\|addcore:adder\", which is child of megafunction instantiation \"lpm_add_sub:Add1\"" {  } { { "lpm_add_sub.tdf" "" { Text "e:/quartes/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } } { "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:oflow_node lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add1\"" {  } { { "addcore.tdf" "" { Text "e:/quartes/quartus/libraries/megafunctions/addcore.tdf" 97 2 0 } } { "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:result_node lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add1\"" {  } { { "addcore.tdf" "" { Text "e:/quartes/quartus/libraries/megafunctions/addcore.tdf" 202 5 0 } } { "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add1\|addcore:adder\|addcore:adder\[0\] lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add1\|addcore:adder\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add1\"" {  } { { "addcore.tdf" "" { Text "e:/quartes/quartus/libraries/megafunctions/addcore.tdf" 203 10 0 } } { "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add1\|altshift:result_ext_latency_ffs lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add1\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add1\"" {  } { { "lpm_add_sub.tdf" "" { Text "e:/quartes/quartus/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } } { "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_sub:Add2 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add2\"" {  } { { "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_add_sub:Add2 " "Info: Instantiated megafunction \"lpm_add_sub:Add2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 3 " "Info: Parameter \"LPM_WIDTH\" = \"3\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add2\|addcore:adder lpm_add_sub:Add2 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add2\|addcore:adder\", which is child of megafunction instantiation \"lpm_add_sub:Add2\"" {  } { { "lpm_add_sub.tdf" "" { Text "e:/quartes/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } } { "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add2\|addcore:adder\|a_csnbuffer:oflow_node lpm_add_sub:Add2 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add2\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"lpm_add_sub:Add2\"" {  } { { "addcore.tdf" "" { Text "e:/quartes/quartus/libraries/megafunctions/addcore.tdf" 97 2 0 } } { "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add2\|addcore:adder\|a_csnbuffer:result_node lpm_add_sub:Add2 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add2\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"lpm_add_sub:Add2\"" {  } { { "addcore.tdf" "" { Text "e:/quartes/quartus/libraries/megafunctions/addcore.tdf" 202 5 0 } } { "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add2\|addcore:adder\|addcore:adder\[0\] lpm_add_sub:Add2 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add2\|addcore:adder\|addcore:adder\[0\]\", which is child of megafunction instantiation \"lpm_add_sub:Add2\"" {  } { { "addcore.tdf" "" { Text "e:/quartes/quartus/libraries/megafunctions/addcore.tdf" 203 10 0 } } { "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_add_sub:Add2\|altshift:result_ext_latency_ffs lpm_add_sub:Add2 " "Info: Elaborated megafunction instantiation \"lpm_add_sub:Add2\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"lpm_add_sub:Add2\"" {  } { { "lpm_add_sub.tdf" "" { Text "e:/quartes/quartus/libraries/megafunctions/lpm_add_sub.tdf" 286 2 0 } } { "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/quartes/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 9 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "174 " "Info: Peak virtual memory: 174 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 21 15:14:29 2009 " "Info: Processing ended: Tue Apr 21 15:14:29 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}