ccd.tan.qmsg

本程序通过CPLD不同的波形来控制CCD的驱动

{ "Info" "ITDB_FULL_TCO_RESULT" "clk CLAMP2 clk_tempc 19.500 ns register " "Info: tco from clock \"clk\" to destination pin \"CLAMP2\" through register \"clk_tempc\" is 19.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.100 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 12.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 3.700 ns cnt3\[1\] 2 REG LC9 9 " "Info: 2: + IC(0.000 ns) + CELL(2.200 ns) = 3.700 ns; Loc. = LC9; Fanout = 9; REG Node = 'cnt3\[1\]'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { clk cnt3[1] } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 92 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(3.800 ns) 8.800 ns LessThan1~38 3 COMB SEXP2 1 " "Info: 3: + IC(1.300 ns) + CELL(3.800 ns) = 8.800 ns; Loc. = SEXP2; Fanout = 1; COMB Node = 'LessThan1~38'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "5.100 ns" { cnt3[1] LessThan1~38 } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 101 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.300 ns) 12.100 ns clk_tempc 4 REG LC1 3 " "Info: 4: + IC(0.000 ns) + CELL(3.300 ns) = 12.100 ns; Loc. = LC1; Fanout = 3; REG Node = 'clk_tempc'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "3.300 ns" { LessThan1~38 clk_tempc } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.800 ns ( 89.26 % ) " "Info: Total cell delay = 10.800 ns ( 89.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 10.74 % ) " "Info: Total interconnect delay = 1.300 ns ( 10.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "12.100 ns" { clk cnt3[1] LessThan1~38 clk_tempc } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "12.100 ns" { clk {} clk~out {} cnt3[1] {} LessThan1~38 {} clk_tempc {} } { 0.000ns 0.000ns 0.000ns 1.300ns 0.000ns } { 0.000ns 1.500ns 2.200ns 3.800ns 3.300ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 108 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.800 ns + Longest register pin " "Info: + Longest register to pin delay is 5.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_tempc 1 REG LC1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 3; REG Node = 'clk_tempc'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_tempc } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(4.200 ns) 5.500 ns CLAMP2~9 2 COMB LC3 1 " "Info: 2: + IC(1.300 ns) + CELL(4.200 ns) = 5.500 ns; Loc. = LC3; Fanout = 1; COMB Node = 'CLAMP2~9'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "5.500 ns" { clk_tempc CLAMP2~9 } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 5.800 ns CLAMP2 3 PIN PIN_20 0 " "Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 5.800 ns; Loc. = PIN_20; Fanout = 0; PIN Node = 'CLAMP2'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "0.300 ns" { CLAMP2~9 CLAMP2 } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns ( 77.59 % ) " "Info: Total cell delay = 4.500 ns ( 77.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 22.41 % ) " "Info: Total interconnect delay = 1.300 ns ( 22.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "5.800 ns" { clk_tempc CLAMP2~9 CLAMP2 } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "5.800 ns" { clk_tempc {} CLAMP2~9 {} CLAMP2 {} } { 0.000ns 1.300ns 0.000ns } { 0.000ns 4.200ns 0.300ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "12.100 ns" { clk cnt3[1] LessThan1~38 clk_tempc } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "12.100 ns" { clk {} clk~out {} cnt3[1] {} LessThan1~38 {} clk_tempc {} } { 0.000ns 0.000ns 0.000ns 1.300ns 0.000ns } { 0.000ns 1.500ns 2.200ns 3.800ns 3.300ns } "" } } { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "5.800 ns" { clk_tempc CLAMP2~9 CLAMP2 } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "5.800 ns" { clk_tempc {} CLAMP2~9 {} CLAMP2 {} } { 0.000ns 1.300ns 0.000ns } { 0.000ns 4.200ns 0.300ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "cnt\[0\] start clk -0.700 ns register " "Info: th for register \"cnt\[0\]\" (data pin = \"start\", clock pin = \"clk\") is -0.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.100 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.100 ns cnt\[0\] 2 REG LC18 3 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.100 ns; Loc. = LC18; Fanout = 3; REG Node = 'cnt\[0\]'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { clk cnt[0] } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.100 ns ( 100.00 % ) " "Info: Total cell delay = 2.100 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { clk cnt[0] } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "2.100 ns" { clk {} clk~out {} cnt[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.600ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "2.000 ns + " "Info: + Micro hold delay of destination is 2.000 ns" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.800 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns start 1 PIN PIN_81 12 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_81; Fanout = 12; PIN Node = 'start'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "" { start } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(3.200 ns) 4.800 ns cnt\[0\] 2 REG LC18 3 " "Info: 2: + IC(1.400 ns) + CELL(3.200 ns) = 4.800 ns; Loc. = LC18; Fanout = 3; REG Node = 'cnt\[0\]'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { start cnt[0] } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 70.83 % ) " "Info: Total cell delay = 3.400 ns ( 70.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 29.17 % ) " "Info: Total interconnect delay = 1.400 ns ( 29.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "4.800 ns" { start cnt[0] } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "4.800 ns" { start {} start~out {} cnt[0] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.200ns 3.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { clk cnt[0] } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "2.100 ns" { clk {} clk~out {} cnt[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.600ns } "" } } { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "4.800 ns" { start cnt[0] } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "4.800 ns" { start {} start~out {} cnt[0] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.200ns 3.200ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 4 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "120 " "Info: Peak virtual memory: 120 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 21 15:05:54 2009 " "Info: Processing ended: Tue Apr 21 15:05:54 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}