ccd.tan.qmsg

本程序通过CPLD不同的波形来控制CCD的驱动

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 6 -1 0 } } { "e:/quartes/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartes/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "LessThan1~38 " "Info: Detected gated clock \"LessThan1~38\" as buffer" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 101 -1 0 } } { "e:/quartes/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartes/quartus/bin/Assignment Editor.qase" 1 { { 0 "LessThan1~38" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clk_tempr " "Info: Detected ripple clock \"clk_tempr\" as buffer" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 54 -1 0 } } { "e:/quartes/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartes/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_tempr" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt3\[2\] " "Info: Detected ripple clock \"cnt3\[2\]\" as buffer" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 92 -1 0 } } { "e:/quartes/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartes/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt3\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "cnt3\[1\] " "Info: Detected ripple clock \"cnt3\[1\]\" as buffer" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 92 -1 0 } } { "e:/quartes/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartes/quartus/bin/Assignment Editor.qase" 1 { { 0 "cnt3\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt\[0\] register cnt\[0\] 140.85 MHz 7.1 ns Internal " "Info: Clock \"clk\" has Internal fmax of 140.85 MHz between source register \"cnt\[0\]\" and destination register \"cnt\[0\]\" (period= 7.1 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.500 ns + Longest register register " "Info: + Longest register to register delay is 4.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[0\] 1 REG LC18 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC18; Fanout = 3; REG Node = 'cnt\[0\]'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[0] } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(3.200 ns) 4.500 ns cnt\[0\] 2 REG LC18 3 " "Info: 2: + IC(1.300 ns) + CELL(3.200 ns) = 4.500 ns; Loc. = LC18; Fanout = 3; REG Node = 'cnt\[0\]'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { cnt[0] cnt[0] } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 71.11 % ) " "Info: Total cell delay = 3.200 ns ( 71.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 28.89 % ) " "Info: Total interconnect delay = 1.300 ns ( 28.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { cnt[0] cnt[0] } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "4.500 ns" { cnt[0] {} cnt[0] {} } { 0.000ns 1.300ns } { 0.000ns 3.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.100 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.100 ns cnt\[0\] 2 REG LC18 3 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.100 ns; Loc. = LC18; Fanout = 3; REG Node = 'cnt\[0\]'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { clk cnt[0] } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.100 ns ( 100.00 % ) " "Info: Total cell delay = 2.100 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { clk cnt[0] } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "2.100 ns" { clk {} clk~out {} cnt[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.600ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.100 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.100 ns cnt\[0\] 2 REG LC18 3 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.100 ns; Loc. = LC18; Fanout = 3; REG Node = 'cnt\[0\]'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { clk cnt[0] } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.100 ns ( 100.00 % ) " "Info: Total cell delay = 2.100 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { clk cnt[0] } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "2.100 ns" { clk {} clk~out {} cnt[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.600ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { clk cnt[0] } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "2.100 ns" { clk {} clk~out {} cnt[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.600ns } "" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "2.100 ns" { clk {} clk~out {} cnt[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.600ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { cnt[0] cnt[0] } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "4.500 ns" { cnt[0] {} cnt[0] {} } { 0.000ns 1.300ns } { 0.000ns 3.200ns } "" } } { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { clk cnt[0] } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "2.100 ns" { clk {} clk~out {} cnt[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.600ns } "" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "2.100 ns" { clk {} clk~out {} cnt[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.600ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 1 " "Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "clk_tempr clk_tempc clk 5.9 ns " "Info: Found hold time violation between source  pin or register \"clk_tempr\" and destination pin or register \"clk_tempc\" for clock \"clk\" (Hold time is 5.9 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "10.000 ns + Largest " "Info: + Largest clock skew is 10.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.100 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 12.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 3.700 ns cnt3\[1\] 2 REG LC9 9 " "Info: 2: + IC(0.000 ns) + CELL(2.200 ns) = 3.700 ns; Loc. = LC9; Fanout = 9; REG Node = 'cnt3\[1\]'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { clk cnt3[1] } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 92 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(3.800 ns) 8.800 ns LessThan1~38 3 COMB SEXP2 1 " "Info: 3: + IC(1.300 ns) + CELL(3.800 ns) = 8.800 ns; Loc. = SEXP2; Fanout = 1; COMB Node = 'LessThan1~38'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "5.100 ns" { cnt3[1] LessThan1~38 } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 101 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.300 ns) 12.100 ns clk_tempc 4 REG LC1 3 " "Info: 4: + IC(0.000 ns) + CELL(3.300 ns) = 12.100 ns; Loc. = LC1; Fanout = 3; REG Node = 'clk_tempc'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "3.300 ns" { LessThan1~38 clk_tempc } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.800 ns ( 89.26 % ) " "Info: Total cell delay = 10.800 ns ( 89.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 10.74 % ) " "Info: Total interconnect delay = 1.300 ns ( 10.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "12.100 ns" { clk cnt3[1] LessThan1~38 clk_tempc } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "12.100 ns" { clk {} clk~out {} cnt3[1] {} LessThan1~38 {} clk_tempc {} } { 0.000ns 0.000ns 0.000ns 1.300ns 0.000ns } { 0.000ns 1.500ns 2.200ns 3.800ns 3.300ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.100 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.100 ns clk_tempr 2 REG LC17 4 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.100 ns; Loc. = LC17; Fanout = 4; REG Node = 'clk_tempr'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { clk clk_tempr } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.100 ns ( 100.00 % ) " "Info: Total cell delay = 2.100 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { clk clk_tempr } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "2.100 ns" { clk {} clk~out {} clk_tempr {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.600ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "12.100 ns" { clk cnt3[1] LessThan1~38 clk_tempc } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "12.100 ns" { clk {} clk~out {} cnt3[1] {} LessThan1~38 {} clk_tempc {} } { 0.000ns 0.000ns 0.000ns 1.300ns 0.000ns } { 0.000ns 1.500ns 2.200ns 3.800ns 3.300ns } "" } } { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { clk clk_tempr } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "2.100 ns" { clk {} clk~out {} clk_tempr {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.600ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns - " "Info: - Micro clock to output delay of source is 1.600 ns" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.500 ns - Shortest register register " "Info: - Shortest register to register delay is 4.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_tempr 1 REG LC17 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC17; Fanout = 4; REG Node = 'clk_tempr'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_tempr } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(3.200 ns) 4.500 ns clk_tempc 2 REG LC1 3 " "Info: 2: + IC(1.300 ns) + CELL(3.200 ns) = 4.500 ns; Loc. = LC1; Fanout = 3; REG Node = 'clk_tempc'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { clk_tempr clk_tempc } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 71.11 % ) " "Info: Total cell delay = 3.200 ns ( 71.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 28.89 % ) " "Info: Total interconnect delay = 1.300 ns ( 28.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { clk_tempr clk_tempc } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "4.500 ns" { clk_tempr {} clk_tempc {} } { 0.000ns 1.300ns } { 0.000ns 3.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "2.000 ns + " "Info: + Micro hold delay of destination is 2.000 ns" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 108 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 54 -1 0 } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 108 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0}  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "12.100 ns" { clk cnt3[1] LessThan1~38 clk_tempc } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "12.100 ns" { clk {} clk~out {} cnt3[1] {} LessThan1~38 {} clk_tempc {} } { 0.000ns 0.000ns 0.000ns 1.300ns 0.000ns } { 0.000ns 1.500ns 2.200ns 3.800ns 3.300ns } "" } } { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { clk clk_tempr } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "2.100 ns" { clk {} clk~out {} clk_tempr {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.600ns } "" } } { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { clk_tempr clk_tempc } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "4.500 ns" { clk_tempr {} clk_tempc {} } { 0.000ns 1.300ns } { 0.000ns 3.200ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "cnt\[0\] start clk 3.700 ns register " "Info: tsu for register \"cnt\[0\]\" (data pin = \"start\", clock pin = \"clk\") is 3.700 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.800 ns + Longest pin register " "Info: + Longest pin to register delay is 4.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns start 1 PIN PIN_81 12 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_81; Fanout = 12; PIN Node = 'start'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "" { start } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(3.200 ns) 4.800 ns cnt\[0\] 2 REG LC18 3 " "Info: 2: + IC(1.400 ns) + CELL(3.200 ns) = 4.800 ns; Loc. = LC18; Fanout = 3; REG Node = 'cnt\[0\]'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { start cnt[0] } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns ( 70.83 % ) " "Info: Total cell delay = 3.400 ns ( 70.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 29.17 % ) " "Info: Total interconnect delay = 1.400 ns ( 29.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "4.800 ns" { start cnt[0] } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "4.800 ns" { start {} start~out {} cnt[0] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.200ns 3.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.100 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns clk 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clk'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 2.100 ns cnt\[0\] 2 REG LC18 3 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 2.100 ns; Loc. = LC18; Fanout = 3; REG Node = 'cnt\[0\]'" {  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { clk cnt[0] } "NODE_NAME" } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.100 ns ( 100.00 % ) " "Info: Total cell delay = 2.100 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { clk cnt[0] } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "2.100 ns" { clk {} clk~out {} cnt[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.600ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "4.800 ns" { start cnt[0] } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "4.800 ns" { start {} start~out {} cnt[0] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.200ns 3.200ns } "" } } { "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartes/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { clk cnt[0] } "NODE_NAME" } } { "e:/quartes/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartes/quartus/bin/Technology_Viewer.qrui" "2.100 ns" { clk {} clk~out {} cnt[0] {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.600ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}