prev_cmp_ccd.map.qmsg

本程序通过CPLD不同的波形来控制CCD的驱动

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Web Edition " "Info: Version 8.0 Build 215 05/29/2008 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 21 15:05:40 2009 " "Info: Processing started: Tue Apr 21 15:05:40 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off CCD -c CCD " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CCD -c CCD" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CCD.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file CCD.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CCD-one " "Info: Found design unit 1: CCD-one" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 CCD " "Info: Found entity 1: CCD" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "CCD " "Info: Elaborating entity \"CCD\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_USED_EXPLICIT_DEFAULT_VALUE" "r CCD.vhd(20) " "Warning (10540): VHDL Signal Declaration warning at CCD.vhd(20): used explicit default value for signal \"r\" because signal was never assigned a value" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 20 0 0 } }  } 0 10540 "VHDL Signal Declaration warning at %2!s!: used explicit default value for signal \"%1!s!\" because signal was never assigned a value" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "start CCD.vhd(54) " "Warning (10492): VHDL Process Statement warning at CCD.vhd(54): signal \"start\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 54 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "start CCD.vhd(108) " "Warning (10492): VHDL Process Statement warning at CCD.vhd(108): signal \"start\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 108 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "st CCD.vhd(110) " "Warning (10492): VHDL Process Statement warning at CCD.vhd(110): signal \"st\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 110 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "q2 CCD.vhd(110) " "Warning (10492): VHDL Process Statement warning at CCD.vhd(110): signal \"q2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 110 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "start CCD.vhd(128) " "Warning (10492): VHDL Process Statement warning at CCD.vhd(128): signal \"start\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 128 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "st CCD.vhd(130) " "Warning (10492): VHDL Process Statement warning at CCD.vhd(130): signal \"st\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 130 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "q2 CCD.vhd(130) " "Warning (10492): VHDL Process Statement warning at CCD.vhd(130): signal \"q2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 130 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "q2 CCD.vhd(132) " "Warning (10492): VHDL Process Statement warning at CCD.vhd(132): signal \"q2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 132 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt1\[0\]~43 5 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: \"cnt1\[0\]~43\"" {  } { { "CCD.vhd" "cnt1\[0\]~43" { Text "E:/FPGA practice/CCD/CCD.vhd" 39 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_counter:cnt1_rtl_0 " "Info: Elaborated megafunction instantiation \"lpm_counter:cnt1_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_counter:cnt1_rtl_0 " "Info: Instantiated megafunction \"lpm_counter:cnt1_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 5 " "Info: Parameter \"LPM_WIDTH\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION UP " "Info: Parameter \"LPM_DIRECTION\" = \"UP\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_COUNTER " "Info: Parameter \"LPM_TYPE\" = \"LPM_COUNTER\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "cnt3\[0\] cnt2\[0\] " "Info (13350): Duplicate register \"cnt3\[0\]\" merged to single register \"cnt2\[0\]\"" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 92 -1 0 } }  } 0 13350 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 54 -1 0 } } { "CCD.vhd" "" { Text "E:/FPGA practice/CCD/CCD.vhd" 128 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0 "" 0 0}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "37 " "Info: Implemented 37 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_MCELLS" "20 " "Info: Implemented 20 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_SEXPS" "7 " "Info: Implemented 7 shareable expanders" {  } {  } 0 0 "Implemented %1!d! shareable expanders" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "177 " "Info: Peak virtual memory: 177 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 21 15:05:44 2009 " "Info: Processing ended: Tue Apr 21 15:05:44 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}