ccd.map.rpt

本程序通过CPLD不同的波形来控制CCD的驱动

; aglobal80.inc                    ; yes             ; Megafunction    ; e:/quartes/quartus/libraries/megafunctions/aglobal80.inc           ;
+----------------------------------+-----------------+-----------------+--------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 20                   ;
; Total registers      ; 16                   ;
; I/O pins             ; 8                    ;
; Shareable expanders  ; 7                    ;
; Maximum fan-out node ; clk                  ;
; Maximum fan-out      ; 14                   ;
; Total fan-out        ; 119                  ;
; Average fan-out      ; 3.40                 ;
+----------------------+----------------------+


+----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                          ;
+-----------------------------+------------+------+-----------------------------+--------------+
; Compilation Hierarchy Node  ; Macrocells ; Pins ; Full Hierarchy Name         ; Library Name ;
+-----------------------------+------------+------+-----------------------------+--------------+
; |CCD                        ; 20         ; 8    ; |CCD                        ; work         ;
;    |lpm_counter:cnt1_rtl_0| ; 5          ; 0    ; |CCD|lpm_counter:cnt1_rtl_0 ; work         ;
+-----------------------------+------------+------+-----------------------------+--------------+


+-------------------------------------------------------------+
; Registers Removed During Synthesis                          ;
+---------------------------------------+---------------------+
; Register name                         ; Reason for Removal  ;
+---------------------------------------+---------------------+
; cnt3[0]                               ; Merged with cnt2[0] ;
; Total Number of Removed Registers = 1 ;                     ;
+---------------------------------------+---------------------+


+-----------------------------------------------+
; Source assignments for lpm_counter:cnt1_rtl_0 ;
+---------------------------+-------+------+----+
; Assignment                ; Value ; From ; To ;
+---------------------------+-------+------+----+
; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -  ;
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -  ;
; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -  ;
+---------------------------+-------+------+----+


+-------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:cnt1_rtl_0 ;
+------------------------+-------------------+----------------------------+
; Parameter Name         ; Value             ; Type                       ;
+------------------------+-------------------+----------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY                 ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY               ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE               ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE             ;
; LPM_WIDTH              ; 5                 ; Untyped                    ;
; LPM_DIRECTION          ; UP                ; Untyped                    ;
; LPM_MODULUS            ; 0                 ; Untyped                    ;
; LPM_AVALUE             ; UNUSED            ; Untyped                    ;
; LPM_SVALUE             ; UNUSED            ; Untyped                    ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                    ;
; DEVICE_FAMILY          ; MAX7000S          ; Untyped                    ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                    ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH         ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK         ;
; CARRY_CNT_EN           ; SMART             ; Untyped                    ;
; LABWIDE_SCLR           ; ON                ; Untyped                    ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                    ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                    ;
+------------------------+-------------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 215 05/29/2008 SJ Web Edition
    Info: Processing started: Tue Apr 21 15:14:11 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CCD -c CCD
Info: Found 2 design units, including 1 entities, in source file CCD.vhd
    Info: Found design unit 1: CCD-one
    Info: Found entity 1: CCD
Info: Elaborating entity "CCD" for the top level hierarchy
Warning (10540): VHDL Signal Declaration warning at CCD.vhd(20): used explicit default value for signal "r" because signal was never assigned a value
Warning (10492): VHDL Process Statement warning at CCD.vhd(54): signal "start" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at CCD.vhd(108): signal "start" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at CCD.vhd(110): signal "st" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at CCD.vhd(110): signal "q2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at CCD.vhd(128): signal "start" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at CCD.vhd(130): signal "st" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at CCD.vhd(130): signal "q2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at CCD.vhd(132): signal "q2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: "cnt1[0]~43"
Info: Elaborated megafunction instantiation "lpm_counter:cnt1_rtl_0"
Info: Instantiated megafunction "lpm_counter:cnt1_rtl_0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "5"
    Info: Parameter "LPM_DIRECTION" = "UP"
    Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Duplicate registers merged to single register
    Info (13350): Duplicate register "cnt3[0]" merged to single register "cnt2[0]"
Info: Registers with preset signals will power-up high
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clk" to global clock signal
Info: Implemented 35 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 6 output pins
    Info: Implemented 20 macrocells
    Info: Implemented 7 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings
    Info: Peak virtual memory: 177 megabytes
    Info: Processing ended: Tue Apr 21 15:14:15 2009
    Info: Elapsed time: 00:00:04
    Info: Total CPU time (on all processors): 00:00:03