regsettings_link.lst

这个程序用于单片机和无线传输芯片CC2500之间的传送

C51 COMPILER V8.17   REGSETTINGS_LINK                                                      03/05/2009 21:30:24 PAGE 1   


C51 COMPILER V8.17, COMPILATION OF MODULE REGSETTINGS_LINK
OBJECT MODULE PLACED IN .\objects\RegSettings_Link.obj
COMPILER INVOKED BY: d:\Keil\C51\BIN\C51.EXE RegSettings_Link.c OMF2 BROWSE INCDIR(..\..\..\..\..\Inc;..\..\..\..\..\lib
                    -) DEFINE(FREQ_2_4,STAND_ALONE) DEBUG PRINT(.\listings\RegSettings_Link.lst) OBJECT(.\objects\RegSettings_Link.obj)

line level    source

   1          /*******************************************************************************************************
   2           *                                                                                                     *
   3           *        **********                                                                                   *
   4           *       ************                                                                                  *
   5           *      ***        ***                                                                                 *
   6           *      ***   +++   ***                                                                                *
   7           *      ***   + +   ***     This file register settings for the 5 different frequency band             *
   8           *      ***   +             supported by CCxx00.                                                       *
   9           *      ***   + +   ***                                                                                *
  10           *      ***   +++   ***     RegSettings_Link.c                                                         *
  11           *      ***        ***                                                                                 *
  12           *       ************                                                                                  *
  13           *        **********                                                                                   *
  14           *                                                                                                     *
  15           *******************************************************************************************************
  16           * Compiler:                Keil C51 V7.50                                                             *
  17           * Target platform:         Chipcon CCxxx0 (Silabs F320)                                               *
  18           * Author:                  SNA                                                                        *
  19           *******************************************************************************************************
  20           * Revision history:     See end of file                                                               *
  21           *******************************************************************************************************/
  22          #include <Chipcon\srf04\regssrf04.h>
  23          #include <Chipcon\srf04\halsrf04.h>
  24          #include <Chipcon\srf04\ebsrf04.h>
  25          
  26          
  27          
  28          
  29          
  30          //-------------------------------------------------------------------------------------------------------
  31          #ifdef FREQ_2_4
  32          // Chipcon
  33          // Product = CC2500
  34          // Chip version = E   (VERSION = 0x03)
  35          // Crystal accuracy = 10 ppm
  36          // X-tal frequency = 26 MHz
  37          // RF output power = 0 dBm
  38          // RX filterbandwidth = 541.666667 kHz
  39          // Phase = 1
  40          // Datarate = 249.938965 kBaud
  41          // Modulation = (7) MSK
  42          // Manchester enable = (0) Manchester disabled
  43          // RF Frequency = 2432.999908 MHz
  44          // Channel spacing = 199.951172 kHz
  45          // Channel number = 0
  46          // Optimization = Sensitivity
  47          // Sync mode = (3) 30/32 sync word bits detected
  48          // Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
  49          // CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
  50          // Forward Error Correction = (0) FEC disabled
  51          // Length configuration = (1) Variable length packets, packet length configured by the first received byte
             - after sync word.
  52          // Packetlength = 255
  53          // Preamble count = (2)  4 bytes
C51 COMPILER V8.17   REGSETTINGS_LINK                                                      03/05/2009 21:30:24 PAGE 2   

  54          // Append status = 1
  55          // Address check = (0) No address check
  56          // FIFO autoflush = 0
  57          // Device address = 0
  58          // GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end
             - of the packet
  59          // GDO2 signal selection = (41) CHIP_RDY
  60          RF_SETTINGS code rfSettings = {
  61              0x07,   // FSCTRL1   Frequency synthesizer control.
  62              0x00,   // FSCTRL0   Frequency synthesizer control.
  63              0x5D,   // FREQ2     Frequency control word, high byte.
  64              0x93,   // FREQ1     Frequency control word, middle byte.
  65              0xB1,   // FREQ0     Frequency control word, low byte.
  66              0x2D,   // MDMCFG4   Modem configuration.
  67              0x3B,   // MDMCFG3   Modem configuration.
  68              0x73,   // MDMCFG2   Modem configuration.
  69              0x22,   // MDMCFG1   Modem configuration.
  70              0xF8,   // MDMCFG0   Modem configuration.
  71              0x00,   // CHANNR    Channel number.
  72              0x01,   // DEVIATN   Modem deviation setting (when FSK modulation is enabled).
  73              0xB6,   // FREND1    Front end RX configuration.
  74              0x10,   // FREND0    Front end RX configuration.
  75              0x18,   // MCSM0     Main Radio Control State Machine configuration.
  76              0x1D,   // FOCCFG    Frequency Offset Compensation Configuration.
  77              0x1C,   // BSCFG     Bit synchronization Configuration.
  78              0xC7,   // AGCCTRL2  AGC control.
  79              0x00,   // AGCCTRL1  AGC control.
  80              0xB0,   // AGCCTRL0  AGC control.
  81              0xEA,   // FSCAL3    Frequency synthesizer calibration.
  82              0x0A,   // FSCAL2    Frequency synthesizer calibration.
  83              0x00,   // FSCAL1    Frequency synthesizer calibration.
  84              0x11,   // FSCAL0    Frequency synthesizer calibration.
  85              0x59,   // FSTEST    Frequency synthesizer calibration.
  86              0x88,   // TEST2     Various test settings.
  87              0x31,   // TEST1     Various test settings.
  88              0x0B,   // TEST0     Various test settings.
  89              0x07,   // FIFOTHR   RXFIFO and TXFIFO thresholds.
  90              0x29,   // IOCFG2    GDO2 output pin configuration.
  91              0x06,   // IOCFG0D   GDO0 output pin configuration. Refer to SmartRF