adc_test.map.qmsg

这是sd/mmc卡程序的第三部分

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 01 14:17:09 2008 " "Info: Processing started: Tue Apr 01 14:17:09 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off adc_test -c adc_test " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adc_test -c adc_test" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "adc_base.v(141) " "Warning (10268): Verilog HDL information at adc_base.v(141): Always Construct contains both blocking and non-blocking assignments" {  } { { "adc_base.v" "" { Text "D:/adc_test/adc_base.v" 141 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adc_base.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file adc_base.v" { { "Info" "ISGN_ENTITY_NAME" "1 adc_base " "Info: Found entity 1: adc_base" {  } { { "adc_base.v" "" { Text "D:/adc_test/adc_base.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adc_test.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file adc_test.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 adc_test " "Info: Found entity 1: adc_test" {  } { { "adc_test.bdf" "" { Schematic "D:/adc_test/adc_test.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "adc_test " "Info: Elaborating entity \"adc_test\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adc_base adc_base:inst " "Info: Elaborating entity \"adc_base\" for hierarchy \"adc_base:inst\"" {  } { { "adc_test.bdf" "inst" { Schematic "D:/adc_test/adc_test.bdf" { { 168 248 424 296 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_signaltap_pack " "Info: Found design unit 1: sld_signaltap_pack" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" 62 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_signaltap-rtl " "Info: Found design unit 2: sld_signaltap-rtl" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" 175 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_signaltap " "Info: Found entity 1: sld_signaltap" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" 85 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}