adc_test.tan.qmsg

这是sd/mmc卡程序的第三部分

{ "Info" "ITDB_TSU_RESULT" "adc_base:inst\|recv_data_r\[1\] sdo sclk 4.680 ns register " "Info: tsu for register \"adc_base:inst\|recv_data_r\[1\]\" (data pin = \"sdo\", clock pin = \"sclk\") is 4.680 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.691 ns + Longest pin register " "Info: + Longest pin to register delay is 8.691 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.954 ns) 0.954 ns sdo 1 PIN PIN_AB20 2 " "Info: 1: + IC(0.000 ns) + CELL(0.954 ns) = 0.954 ns; Loc. = PIN_AB20; Fanout = 2; PIN Node = 'sdo'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sdo } "NODE_NAME" } } { "adc_test.bdf" "" { Schematic "D:/adc_test/adc_test.bdf" { { 240 -8 160 256 "sdo" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.423 ns) + CELL(0.206 ns) 8.583 ns adc_base:inst\|recv_data_r\[1\]~feeder 2 COMB LCCOMB_X46_Y6_N8 1 " "Info: 2: + IC(7.423 ns) + CELL(0.206 ns) = 8.583 ns; Loc. = LCCOMB_X46_Y6_N8; Fanout = 1; COMB Node = 'adc_base:inst\|recv_data_r\[1\]~feeder'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.629 ns" { sdo adc_base:inst|recv_data_r[1]~feeder } "NODE_NAME" } } { "adc_base.v" "" { Text "D:/adc_test/adc_base.v" 143 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.691 ns adc_base:inst\|recv_data_r\[1\] 3 REG LCFF_X46_Y6_N9 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.691 ns; Loc. = LCFF_X46_Y6_N9; Fanout = 2; REG Node = 'adc_base:inst\|recv_data_r\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { adc_base:inst|recv_data_r[1]~feeder adc_base:inst|recv_data_r[1] } "NODE_NAME" } } { "adc_base.v" "" { Text "D:/adc_test/adc_base.v" 143 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.268 ns ( 14.59 % ) " "Info: Total cell delay = 1.268 ns ( 14.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.423 ns ( 85.41 % ) " "Info: Total interconnect delay = 7.423 ns ( 85.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.691 ns" { sdo adc_base:inst|recv_data_r[1]~feeder adc_base:inst|recv_data_r[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.691 ns" { sdo sdo~combout adc_base:inst|recv_data_r[1]~feeder adc_base:inst|recv_data_r[1] } { 0.000ns 0.000ns 7.423ns 0.000ns } { 0.000ns 0.954ns 0.206ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "adc_base.v" "" { Text "D:/adc_test/adc_base.v" 143 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk destination 3.971 ns - Shortest register " "Info: - Shortest clock path from clock \"sclk\" to destination register is 3.971 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.935 ns) 0.935 ns sclk 1 CLK PIN_V21 510 " "Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_V21; Fanout = 510; CLK Node = 'sclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "adc_test.bdf" "" { Schematic "D:/adc_test/adc_test.bdf" { { 224 -8 160 240 "sclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.370 ns) + CELL(0.666 ns) 3.971 ns adc_base:inst\|recv_data_r\[1\] 2 REG LCFF_X46_Y6_N9 2 " "Info: 2: + IC(2.370 ns) + CELL(0.666 ns) = 3.971 ns; Loc. = LCFF_X46_Y6_N9; Fanout = 2; REG Node = 'adc_base:inst\|recv_data_r\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.036 ns" { sclk adc_base:inst|recv_data_r[1] } "NODE_NAME" } } { "adc_base.v" "" { Text "D:/adc_test/adc_base.v" 143 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.601 ns ( 40.32 % ) " "Info: Total cell delay = 1.601 ns ( 40.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.370 ns ( 59.68 % ) " "Info: Total interconnect delay = 2.370 ns ( 59.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.971 ns" { sclk adc_base:inst|recv_data_r[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.971 ns" { sclk sclk~combout adc_base:inst|recv_data_r[1] } { 0.000ns 0.000ns 2.370ns } { 0.000ns 0.935ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.691 ns" { sdo adc_base:inst|recv_data_r[1]~feeder adc_base:inst|recv_data_r[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.691 ns" { sdo sdo~combout adc_base:inst|recv_data_r[1]~feeder adc_base:inst|recv_data_r[1] } { 0.000ns 0.000ns 7.423ns 0.000ns } { 0.000ns 0.954ns 0.206ns 0.108ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.971 ns" { sclk adc_base:inst|recv_data_r[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.971 ns" { sclk sclk~combout adc_base:inst|recv_data_r[1] } { 0.000ns 0.000ns 2.370ns } { 0.000ns 0.935ns 0.666ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "sclk sdi adc_base:inst\|sdi_r 11.588 ns register " "Info: tco from clock \"sclk\" to destination pin \"sdi\" through register \"adc_base:inst\|sdi_r\" is 11.588 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk source 4.435 ns + Longest register " "Info: + Longest clock path from clock \"sclk\" to source register is 4.435 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.935 ns) 0.935 ns sclk 1 CLK PIN_V21 510 " "Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_V21; Fanout = 510; CLK Node = 'sclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "adc_test.bdf" "" { Schematic "D:/adc_test/adc_test.bdf" { { 224 -8 160 240 "sclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.834 ns) + CELL(0.666 ns) 4.435 ns adc_base:inst\|sdi_r 2 REG LCFF_X40_Y9_N1 2 " "Info: 2: + IC(2.834 ns) + CELL(0.666 ns) = 4.435 ns; Loc. = LCFF_X40_Y9_N1; Fanout = 2; REG Node = 'adc_base:inst\|sdi_r'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { sclk adc_base:inst|sdi_r } "NODE_NAME" } } { "adc_base.v" "" { Text "D:/adc_test/adc_base.v" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.601 ns ( 36.10 % ) " "Info: Total cell delay = 1.601 ns ( 36.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.834 ns ( 63.90 % ) " "Info: Total interconnect delay = 2.834 ns ( 63.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.435 ns" { sclk adc_base:inst|sdi_r } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.435 ns" { sclk sclk~combout adc_base:inst|sdi_r } { 0.000ns 0.000ns 2.834ns } { 0.000ns 0.935ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "adc_base.v" "" { Text "D:/adc_test/adc_base.v" 84 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.849 ns + Longest register pin " "Info: + Longest register to pin delay is 6.849 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns adc_base:inst\|sdi_r 1 REG LCFF_X40_Y9_N1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X40_Y9_N1; Fanout = 2; REG Node = 'adc_base:inst\|sdi_r'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { adc_base:inst|sdi_r } "NODE_NAME" } } { "adc_base.v" "" { Text "D:/adc_test/adc_base.v" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.603 ns) + CELL(3.246 ns) 6.849 ns sdi 2 PIN PIN_AF21 0 " "Info: 2: + IC(3.603 ns) + CELL(3.246 ns) = 6.849 ns; Loc. = PIN_AF21; Fanout = 0; PIN Node = 'sdi'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.849 ns" { adc_base:inst|sdi_r sdi } "NODE_NAME" } } { "adc_test.bdf" "" { Schematic "D:/adc_test/adc_test.bdf" { { 240 480 656 256 "sdi" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.246 ns ( 47.39 % ) " "Info: Total cell delay = 3.246 ns ( 47.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.603 ns ( 52.61 % ) " "Info: Total interconnect delay = 3.603 ns ( 52.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.849 ns" { adc_base:inst|sdi_r sdi } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.849 ns" { adc_base:inst|sdi_r sdi } { 0.000ns 3.603ns } { 0.000ns 3.246ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.435 ns" { sclk adc_base:inst|sdi_r } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.435 ns" { sclk sclk~combout adc_base:inst|sdi_r } { 0.000ns 0.000ns 2.834ns } { 0.000ns 0.935ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.849 ns" { adc_base:inst|sdi_r sdi } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.849 ns" { adc_base:inst|sdi_r sdi } { 0.000ns 3.603ns } { 0.000ns 3.246ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "altera_internal_jtag~TDO altera_reserved_tdo 3.026 ns Longest " "Info: Longest tpd from source pin \"altera_internal_jtag~TDO\" to destination pin \"altera_reserved_tdo\" is 3.026 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDO 1 PIN JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; PIN Node = 'altera_internal_jtag~TDO'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.026 ns) 3.026 ns altera_reserved_tdo 2 PIN PIN_M7 0 " "Info: 2: + IC(0.000 ns) + CELL(3.026 ns) = 3.026 ns; Loc. = PIN_M7; Fanout = 0; PIN Node = 'altera_reserved_tdo'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.026 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.026 ns ( 100.00 % ) " "Info: Total cell delay = 3.026 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.026 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.026 ns" { altera_internal_jtag~TDO altera_reserved_tdo } { 0.000ns 0.000ns } { 0.000ns 3.026ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}