adc_test.tan.qmsg

这是sd/mmc卡程序的第三部分

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "sclk " "Info: Assuming node \"sclk\" is an undefined clock" {  } { { "adc_test.bdf" "" { Schematic "D:/adc_test/adc_test.bdf" { { 224 -8 160 240 "sclk" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sclk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "sclk register sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|is_max_write_address_ff memory sld_signaltap:auto_signaltap_0\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_pti2:auto_generated\|altsyncram_44l1:altsyncram1\|ram_block2a14~portb_we_reg 140.53 MHz 7.116 ns Internal " "Info: Clock \"sclk\" has Internal fmax of 140.53 MHz between source register \"sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|is_max_write_address_ff\" and destination memory \"sld_signaltap:auto_signaltap_0\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_pti2:auto_generated\|altsyncram_44l1:altsyncram1\|ram_block2a14~portb_we_reg\" (period= 7.116 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.000 ns + Longest register memory " "Info: + Longest register to memory delay is 7.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|is_max_write_address_ff 1 REG LCFF_X42_Y14_N19 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X42_Y14_N19; Fanout = 7; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|is_max_write_address_ff'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_max_write_address_ff } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_acquisition_buffer.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_acquisition_buffer.vhd" 139 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.133 ns) + CELL(0.370 ns) 2.503 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out~116 2 COMB LCCOMB_X51_Y11_N28 3 " "Info: 2: + IC(2.133 ns) + CELL(0.370 ns) = 2.503 ns; Loc. = LCCOMB_X51_Y11_N28; Fanout = 3; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_seg_state_machine:sm2\|status_out~116'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.503 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_max_write_address_ff sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~116 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_ela_control.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_ela_control.vhd" 1193 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.367 ns) + CELL(0.206 ns) 3.076 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|buffer_write_ena_int~43 3 COMB LCCOMB_X51_Y11_N30 300 " "Info: 3: + IC(0.367 ns) + CELL(0.206 ns) = 3.076 ns; Loc. = LCCOMB_X51_Y11_N30; Fanout = 300; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|buffer_write_ena_int~43'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.573 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~116 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|buffer_write_ena_int~43 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.099 ns) + CELL(0.825 ns) 7.000 ns sld_signaltap:auto_signaltap_0\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_pti2:auto_generated\|altsyncram_44l1:altsyncram1\|ram_block2a14~portb_we_reg 4 MEM M4K_X26_Y6 0 " "Info: 4: + IC(3.099 ns) + CELL(0.825 ns) = 7.000 ns; Loc. = M4K_X26_Y6; Fanout = 0; MEM Node = 'sld_signaltap:auto_signaltap_0\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_pti2:auto_generated\|altsyncram_44l1:altsyncram1\|ram_block2a14~portb_we_reg'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.924 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|buffer_write_ena_int~43 sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_pti2:auto_generated|altsyncram_44l1:altsyncram1|ram_block2a14~portb_we_reg } "NODE_NAME" } } { "db/altsyncram_44l1.tdf" "" { Text "D:/adc_test/db/altsyncram_44l1.tdf" 458 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.401 ns ( 20.01 % ) " "Info: Total cell delay = 1.401 ns ( 20.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.599 ns ( 79.99 % ) " "Info: Total interconnect delay = 5.599 ns ( 79.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.000 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_max_write_address_ff sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~116 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|buffer_write_ena_int~43 sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_pti2:auto_generated|altsyncram_44l1:altsyncram1|ram_block2a14~portb_we_reg } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.000 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_max_write_address_ff sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~116 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|buffer_write_ena_int~43 sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_pti2:auto_generated|altsyncram_44l1:altsyncram1|ram_block2a14~portb_we_reg } { 0.000ns 2.133ns 0.367ns 3.099ns } { 0.000ns 0.370ns 0.206ns 0.825ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.234 ns - Smallest " "Info: - Smallest clock skew is 0.234 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk destination 5.126 ns + Shortest memory " "Info: + Shortest clock path from clock \"sclk\" to destination memory is 5.126 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.935 ns) 0.935 ns sclk 1 CLK PIN_V21 510 " "Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_V21; Fanout = 510; CLK Node = 'sclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "adc_test.bdf" "" { Schematic "D:/adc_test/adc_test.bdf" { { 224 -8 160 240 "sclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.313 ns) + CELL(0.878 ns) 5.126 ns sld_signaltap:auto_signaltap_0\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_pti2:auto_generated\|altsyncram_44l1:altsyncram1\|ram_block2a14~portb_we_reg 2 MEM M4K_X26_Y6 0 " "Info: 2: + IC(3.313 ns) + CELL(0.878 ns) = 5.126 ns; Loc. = M4K_X26_Y6; Fanout = 0; MEM Node = 'sld_signaltap:auto_signaltap_0\|altsyncram:\\stp_non_zero_ram_gen:stp_buffer_ram\|altsyncram_pti2:auto_generated\|altsyncram_44l1:altsyncram1\|ram_block2a14~portb_we_reg'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.191 ns" { sclk sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_pti2:auto_generated|altsyncram_44l1:altsyncram1|ram_block2a14~portb_we_reg } "NODE_NAME" } } { "db/altsyncram_44l1.tdf" "" { Text "D:/adc_test/db/altsyncram_44l1.tdf" 458 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.813 ns ( 35.37 % ) " "Info: Total cell delay = 1.813 ns ( 35.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.313 ns ( 64.63 % ) " "Info: Total interconnect delay = 3.313 ns ( 64.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.126 ns" { sclk sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_pti2:auto_generated|altsyncram_44l1:altsyncram1|ram_block2a14~portb_we_reg } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.126 ns" { sclk sclk~combout sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_pti2:auto_generated|altsyncram_44l1:altsyncram1|ram_block2a14~portb_we_reg } { 0.000ns 0.000ns 3.313ns } { 0.000ns 0.935ns 0.878ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk source 4.892 ns - Longest register " "Info: - Longest clock path from clock \"sclk\" to source register is 4.892 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.935 ns) 0.935 ns sclk 1 CLK PIN_V21 510 " "Info: 1: + IC(0.000 ns) + CELL(0.935 ns) = 0.935 ns; Loc. = PIN_V21; Fanout = 510; CLK Node = 'sclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "adc_test.bdf" "" { Schematic "D:/adc_test/adc_test.bdf" { { 224 -8 160 240 "sclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.291 ns) + CELL(0.666 ns) 4.892 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|is_max_write_address_ff 2 REG LCFF_X42_Y14_N19 7 " "Info: 2: + IC(3.291 ns) + CELL(0.666 ns) = 4.892 ns; Loc. = LCFF_X42_Y14_N19; Fanout = 7; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|is_max_write_address_ff'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.957 ns" { sclk sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_max_write_address_ff } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_acquisition_buffer.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_acquisition_buffer.vhd" 139 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.601 ns ( 32.73 % ) " "Info: Total cell delay = 1.601 ns ( 32.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.291 ns ( 67.27 % ) " "Info: Total interconnect delay = 3.291 ns ( 67.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.892 ns" { sclk sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_max_write_address_ff } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.892 ns" { sclk sclk~combout sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_max_write_address_ff } { 0.000ns 0.000ns 3.291ns } { 0.000ns 0.935ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.126 ns" { sclk sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_pti2:auto_generated|altsyncram_44l1:altsyncram1|ram_block2a14~portb_we_reg } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.126 ns" { sclk sclk~combout sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_pti2:auto_generated|altsyncram_44l1:altsyncram1|ram_block2a14~portb_we_reg } { 0.000ns 0.000ns 3.313ns } { 0.000ns 0.935ns 0.878ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.892 ns" { sclk sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_max_write_address_ff } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.892 ns" { sclk sclk~combout sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_max_write_address_ff } { 0.000ns 0.000ns 3.291ns } { 0.000ns 0.935ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_acquisition_buffer.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_acquisition_buffer.vhd" 139 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_44l1.tdf" "" { Text "D:/adc_test/db/altsyncram_44l1.tdf" 458 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.000 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_max_write_address_ff sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~116 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|buffer_write_ena_int~43 sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_pti2:auto_generated|altsyncram_44l1:altsyncram1|ram_block2a14~portb_we_reg } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.000 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_max_write_address_ff sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out~116 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|buffer_write_ena_int~43 sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_pti2:auto_generated|altsyncram_44l1:altsyncram1|ram_block2a14~portb_we_reg } { 0.000ns 2.133ns 0.367ns 3.099ns } { 0.000ns 0.370ns 0.206ns 0.825ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.126 ns" { sclk sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_pti2:auto_generated|altsyncram_44l1:altsyncram1|ram_block2a14~portb_we_reg } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.126 ns" { sclk sclk~combout sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_pti2:auto_generated|altsyncram_44l1:altsyncram1|ram_block2a14~portb_we_reg } { 0.000ns 0.000ns 3.313ns } { 0.000ns 0.935ns 0.878ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.892 ns" { sclk sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_max_write_address_ff } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.892 ns" { sclk sclk~combout sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_max_write_address_ff } { 0.000ns 0.000ns 3.291ns } { 0.000ns 0.935ns 0.666ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 register sld_hub:sld_hub_inst\|hub_tdo 142.45 MHz 7.02 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 142.45 MHz between source register \"sld_hub:sld_hub_inst\|jtag_debug_mode_usr1\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 7.02 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.250 ns + Longest register register " "Info: + Longest register to register delay is 3.250 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 1 REG LCFF_X34_Y17_N27 24 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X34_Y17_N27; Fanout = 24; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 391 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.221 ns) + CELL(0.537 ns) 1.758 ns sld_hub:sld_hub_inst\|hub_tdo~454 2 COMB LCCOMB_X36_Y17_N20 1 " "Info: 2: + IC(1.221 ns) + CELL(0.537 ns) = 1.758 ns; Loc. = LCCOMB_X36_Y17_N20; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~454'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.758 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|hub_tdo~454 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.014 ns) + CELL(0.370 ns) 3.142 ns sld_hub:sld_hub_inst\|hub_tdo~455 3 COMB LCCOMB_X35_Y18_N10 1 " "Info: 3: + IC(1.014 ns) + CELL(0.370 ns) = 3.142 ns; Loc. = LCCOMB_X35_Y18_N10; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~455'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.384 ns" { sld_hub:sld_hub_inst|hub_tdo~454 sld_hub:sld_hub_inst|hub_tdo~455 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.250 ns sld_hub:sld_hub_inst\|hub_tdo 4 REG LCFF_X35_Y18_N11 2 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 3.250 ns; Loc. = LCFF_X35_Y18_N11; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { sld_hub:sld_hub_inst|hub_tdo~455 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.015 ns ( 31.23 % ) " "Info: Total cell delay = 1.015 ns ( 31.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.235 ns ( 68.77 % ) " "Info: Total interconnect delay = 2.235 ns ( 68.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.250 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|hub_tdo~454 sld_hub:sld_hub_inst|hub_tdo~455 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.250 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|hub_tdo~454 sld_hub:sld_hub_inst|hub_tdo~455 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.221ns 1.014ns 0.000ns } { 0.000ns 0.537ns 0.370ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.004 ns - Smallest " "Info: - Smallest clock skew is 0.004 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.670 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.670 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.816 ns) + CELL(0.000 ns) 3.816 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G3 465 " "Info: 2: + IC(3.816 ns) + CELL(0.000 ns) = 3.816 ns; Loc. = CLKCTRL_G3; Fanout = 465; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.816 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.188 ns) + CELL(0.666 ns) 5.670 ns sld_hub:sld_hub_inst\|hub_tdo 3 REG LCFF_X35_Y18_N11 2 " "Info: 3: + IC(1.188 ns) + CELL(0.666 ns) = 5.670 ns; Loc. = LCFF_X35_Y18_N11; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.854 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 11.75 % ) " "Info: Total cell delay = 0.666 ns ( 11.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.004 ns ( 88.25 % ) " "Info: Total interconnect delay = 5.004 ns ( 88.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.670 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.670 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 3.816ns 1.188ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.666 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.666 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.816 ns) + CELL(0.000 ns) 3.816 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G3 465 " "Info: 2: + IC(3.816 ns) + CELL(0.000 ns) = 3.816 ns; Loc. = CLKCTRL_G3; Fanout = 465; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.816 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.184 ns) + CELL(0.666 ns) 5.666 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 3 REG LCFF_X34_Y17_N27 24 " "Info: 3: + IC(1.184 ns) + CELL(0.666 ns) = 5.666 ns; Loc. = LCFF_X34_Y17_N27; Fanout = 24; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.850 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 391 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 11.75 % ) " "Info: Total cell delay = 0.666 ns ( 11.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.000 ns ( 88.25 % ) " "Info: Total interconnect delay = 5.000 ns ( 88.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.666 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.666 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 3.816ns 1.184ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.670 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.670 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 3.816ns 1.188ns } { 0.000ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.666 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.666 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 3.816ns 1.184ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 391 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 391 -1 0 } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.250 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|hub_tdo~454 sld_hub:sld_hub_inst|hub_tdo~455 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.250 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|hub_tdo~454 sld_hub:sld_hub_inst|hub_tdo~455 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.221ns 1.014ns 0.000ns } { 0.000ns 0.537ns 0.370ns 0.108ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.670 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.670 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 3.816ns 1.188ns } { 0.000ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.666 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.666 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } { 0.000ns 3.816ns 1.184ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}