adc_base.v

这是sd/mmc卡程序的第三部分

module adc_base(                             
	    ad_enable,                         //与寄存器文件的接口
	    reset1_n, 
	    rev_data,
	                               
	    reset2_n,                           //与ad73360的接口
	    se,
	    sclk,
	    sdi,
	    sdo,
	    sdofs,
	    data_ready
	    );
     
        //Inputs	
	    input ad_enable;			
	    input reset1_n;				

	    //Outputs
	    output[15:0] rev_data;				

		//Inputs
	    input sclk;					
	    input sdo;
	    input sdofs;								

	    //Outputs					
	    output sdi;					
	    output reset2_n;
	    output se;		
	    output data_ready;

parameter all_data=160'h8103_8201_8308_8400_8500_8681_8700_8001_7fff_ffff;
reg [3:0] counter;
reg [15:0] cmd_data;
reg data_ready;

//输出数据状态机的状态
parameter idle=           2'h0;
parameter spi_shift0=     2'h1;
parameter spi_shift1=     2'h2;
parameter spi_shift_comp= 2'h3;

//输出数据的寄存器定义
reg [1:0]	spi_sta;
reg sdi_r;
reg [4:0]	spi_count;
reg [15:0]  send_data_r;

//输入数据状态机的状态
parameter ready=          2'h0;
parameter spi_shift2=     2'h1;
parameter spi_shift3=     2'h2;
parameter spi_shift_fini= 2'h3;

//输入数据的寄存器定义

reg [1:0]	spi_sta1;
reg sdo_r;
reg [4:0]	spi_count1;
reg [16:0]  recv_data_r;
reg [15:0]  recv_temp;

always @(counter)
begin
          case(counter)
            4'd0: cmd_data<=all_data[159:144];
            4'd1: cmd_data<=all_data[143:128];
            4'd2: cmd_data<=all_data[127:112];
            4'd3: cmd_data<=all_data[111:96];
            4'd4: cmd_data<=all_data[95:80];
            4'd5: cmd_data<=all_data[79:64];
            4'd6: cmd_data<=all_data[63:48];
            4'd7: cmd_data<=all_data[47:32];
            4'd8: cmd_data<=all_data[31:16];
            4'd9: cmd_data<=all_data[15:0];
            default:cmd_data<=16'hffff;
	      endcase
end

//输出数据状态机
always @(posedge sclk or negedge reset1_n)
begin
	if(~reset1_n)
	begin
	  spi_sta<=idle;
	end
	else if(ad_enable)
	begin
		case(spi_sta)
		idle:
		begin
			spi_count<=5'h0;
			send_data_r<=cmd_data;
			spi_sta<=spi_shift0;
		end
				
		spi_shift0:
		begin
		  if(sdofs==1'b1)
		     begin
			   spi_sta<=spi_shift1;
			 end
		  else
		     spi_sta<=spi_shift0;
		end
				
		spi_shift1:
		begin
			sdi_r<=send_data_r[15];
			send_data_r<={send_data_r[14:0],1'b0};             	
			spi_count<=spi_count + 5'h1;
			spi_sta<=spi_shift_comp;
		end
				
		spi_shift_comp:
		begin
			if (spi_count==5'd16)         //连续发送16位数据
                        begin
                            if(counter==4'd9)
                                spi_sta<=spi_shift_comp;
                            else
                              begin
                                 counter<=counter+1'b1;
                                 spi_sta<=idle;
                              end
                        end
			else
				spi_sta<=spi_shift1;
		end
		default:
		    spi_sta<=idle;
		endcase
	end
end

assign sdi=sdi_r;
assign se=1'b1;

//输入数据状态机
always @(negedge sclk or negedge reset1_n)
begin
	if(~reset1_n)
	begin
	  spi_sta1<=ready;
	end
	else if(ad_enable)
	begin
	    data_ready<=1'b0;
		case(spi_sta1)
		ready:
		begin
			spi_count1<=5'h0;
			spi_sta1<=spi_shift2;
		end
				
		spi_shift2:
		begin
			if(sdofs==1'b1)
			  spi_sta1<=spi_shift3;
			else
			  spi_sta1<=spi_shift2;
		end
				
		spi_shift3:
		begin
			recv_data_r[0]=sdo;
			recv_data_r<={recv_data_r[15:0],1'b0};             	
			spi_count1<=spi_count1 + 5'h1;
			spi_sta1<=spi_shift_fini;
		end
				
		spi_shift_fini:
		begin
			if (spi_count1==5'd16)         //连续接收16位数据
            begin
				recv_temp<=recv_data_r[16:1];
				spi_sta1<=ready;
				data_ready<=1'b1;
			end
			else
				spi_sta1<=spi_shift3;
		end
		default:
		    spi_sta1<=ready;
		endcase
	end
end

assign rev_data=recv_temp;
assign reset2_n=reset1_n;

endmodule