adc_test.map.rpt

这是sd/mmc卡程序的第三部分

+----------------------------------------------------------------------------------------------------------------+
; State Machine - |adc_test|adc_base:inst|spi_sta1                                                               ;
+-------------------------+-------------------------+---------------------+---------------------+----------------+
; Name                    ; spi_sta1.spi_shift_fini ; spi_sta1.spi_shift2 ; spi_sta1.spi_shift3 ; spi_sta1.ready ;
+-------------------------+-------------------------+---------------------+---------------------+----------------+
; spi_sta1.ready          ; 0                       ; 0                   ; 0                   ; 0              ;
; spi_sta1.spi_shift3     ; 0                       ; 0                   ; 1                   ; 1              ;
; spi_sta1.spi_shift2     ; 0                       ; 1                   ; 0                   ; 1              ;
; spi_sta1.spi_shift_fini ; 1                       ; 0                   ; 0                   ; 1              ;
+-------------------------+-------------------------+---------------------+---------------------+----------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 435   ;
; Number of registers using Synchronous Clear  ; 14    ;
; Number of registers using Synchronous Load   ; 24    ;
; Number of registers using Asynchronous Clear ; 243   ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 242   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; sld_hub:sld_hub_inst|hub_tdo           ; 2       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                               ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------+
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |adc_test|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1]                             ;
; 3:1                ; 14 bits   ; 28 LEs        ; 14 LEs               ; 14 LEs                 ; Yes        ; |adc_test|adc_base:inst|send_data_r[7]                                         ;
; 5:1                ; 5 bits    ; 15 LEs        ; 5 LEs                ; 10 LEs                 ; Yes        ; |adc_test|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]         ;
; 20:1               ; 4 bits    ; 52 LEs        ; 36 LEs               ; 16 LEs                 ; Yes        ; |adc_test|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[3]              ;
; 5:1                ; 4 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |adc_test|sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|word_counter[0] ;
; 12:1               ; 4 bits    ; 32 LEs        ; 24 LEs               ; 8 LEs                  ; Yes        ; |adc_test|sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[3]      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------+


+-------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0 ;
+---------------------------------+-------+------+------+
; Assignment                      ; Value ; From ; To   ;
+---------------------------------+-------+------+------+
; NOT_GATE_PUSH_BACK              ; OFF   ; -    ; -    ;
; POWER_UP_LEVEL                  ; LOW   ; -    ; -    ;
; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF   ; -    ; -    ;
+---------------------------------+-------+------+------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_pti2:auto_generated ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                                     ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                      ;
+---------------------------------+--------------------+------+------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; So