hld.txt

红绿灯Verilog程序 很好很好 很有用的

要求：编写一个交通红绿灯程序，主干道传感器如果测得流量超过20辆/min，则主干道的绿灯亮60s,否则亮40秒，此干道也如此，当次干道传感器如果测得流量超过10辆/min，则次干道的绿灯亮32s,否则亮20秒。

module traffic(N1,N2,G1,G2,R1,R2,Y1,Y2,right1,right2,left1,left2,reset);
input N1,N2,reset;//主次干道传感器，为一时分别表示N1>=20/min,N2>=10/min,reset系统复位键
output G1,G2,R1,R2,Y1,Y2,right1,right2,left1,left2;
reg G1,G2,R1,R2,Y1,Y2,right1,right2,left1,left2;
reg[4:1] state;
parameter s0=4'b0000,s1=4'b0001,s2=4'b0010,s3=4'b0011,s4=4'b0100,s5=4'b0101,s6=4'b0110,s7=4'b0111,s8=4'b1000,s9=4'b1001,s10=4'b1010;
always @(reset or N1 or N2)
begin
  if(reset) 
  begin 
   {G1,G2,R1,R2,Y1,Y2,right1,right2,left1,left2}=10'b0000110000;
   state=s0;
  end
  else
  begin
  case(state)
  s0:begin
      begin
      {G1,G2,R1,R2,Y1,Y2,right1,right2,left1,left2}=10'b0000110000;
      end
      #4;
      if(N1)
      state=s1;
      else
      state=s7;
     end
  s1:begin
     {G1,G2,R1,R2,Y1,Y2,right1,right2,left1,left2}=10'b1001001000;
     #30;
     state=s2;
     end
  s2:begin
     {G1,G2,R1,R2,Y1,Y2,right1,right2,left1,left2}=10'b1001000010;
     #30;
     state=s3;
     end
  s3:begin
      begin
      {G1,G2,R1,R2,Y1,Y2,right1,right2,left1,left2}=10'b0001100000;
      end
      #4;
      if(N2)
      state=s9;
      else
      state=s4;
     end
  s4:begin
     {G1,G2,R1,R2,Y1,Y2,right1,right2,left1,left2}=10'b0110000100;
     #10;
     state=s5;
     end
  s5:begin
     {G1,G2,R1,R2,Y1,Y2,right1,right2,left1,left2}=10'b0110000001;
     #10;
     state=s6;
     end
  s6:begin
      begin
      {G1,G2,R1,R2,Y1,Y2,right1,right2,left1,left2}=10'b0010010000;
      end
      #4;
      if(N1)
      state=s1;
      else
      state=s7;
     end
  s7:begin
     {G1,G2,R1,R2,Y1,Y2,right1,right2,left1,left2}=10'b1001001000;
     #20;
     state=s8;
     end
  s8:begin
     {G1,G2,R1,R2,Y1,Y2,right1,right2,left1,left2}=10'b1001000010;
     #20;
     state=s3;
     end
  s9:begin
     {G1,G2,R1,R2,Y1,Y2,right1,right2,left1,left2}=10'b0110000100;
     #16;
     state=s10;
     end
  s10:begin
     {G1,G2,R1,R2,Y1,Y2,right1,right2,left1,left2}=10'b0110000001;
     #16;
     state=s5;
     end
  default:state=s0;
  endcase
 end
end
endmodule