📄 hx8824.lst
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I2CWriteByte(HX8824_ADDR, 0xD3, 0x63); // M: 100-1
I2CWriteByte(HX8824_ADDR, 0xD4, 0x00); // M
#endif
213 1 //****************************************************************************************
214 1 #if mode6448_6448
// Select source from VGA
bVideo = 0;
S1 = 1;
S2 = 0;
Mode = 2;
I2CWriteByte(HX8824_ADDR, 0x10, 0x1C); // USE EXTERNAL SYNC AND DE
I2CWriteByte(HX8824_ADDR, 0x11, 0x04);
I2CWriteByte(HX8824_ADDR, 0x20, 0x00);
I2CWriteByte(HX8824_ADDR, 0x21, 0x10);
I2CWriteByte(HX8824_ADDR, 0x22, 0xFF);
I2CWriteByte(HX8824_ADDR, 0x23, 0x0F);
I2CWriteByte(HX8824_ADDR, 0x20, 0x00);
I2CWriteByte(HX8824_ADDR, 0x21, 0x10);
I2CWriteByte(HX8824_ADDR, 0x22, 0xFF);
I2CWriteByte(HX8824_ADDR, 0x23, 0x1F);
I2CWriteByte(HX8824_ADDR, 0x24, 0x00);
I2CWriteByte(HX8824_ADDR, 0x25, 0x00);
I2CWriteByte(HX8824_ADDR, 0x24, 0x00);
I2CWriteByte(HX8824_ADDR, 0x25, 0x04);
I2CWriteByte(HX8824_ADDR, 0x27, 0x05); //DELAY
I2CWriteByte(HX8824_ADDR, 0xA0, 0x1E);
I2CWriteByte(HX8824_ADDR, 0xA1, 0x07);
I2CWriteByte(HX8824_ADDR, 0xA2, 0x00);
I2CWriteByte(HX8824_ADDR, 0x00, 0x80);
C51 COMPILER V7.07 HX8824 09/26/2006 08:56:42 PAGE 5
I2CWriteByte(HX8824_ADDR, 0x01, 0x02);
I2CWriteByte(HX8824_ADDR, 0x02, 0xE0);
I2CWriteByte(HX8824_ADDR, 0x03, 0x01);
I2CWriteByte(HX8824_ADDR, 0x90, 0x20);
I2CWriteByte(HX8824_ADDR, 0x91, 0x03);
I2CWriteByte(HX8824_ADDR, 0x92, 0x60);
I2CWriteByte(HX8824_ADDR, 0x93, 0x00);
I2CWriteByte(HX8824_ADDR, 0x94, 0x90);
I2CWriteByte(HX8824_ADDR, 0x95, 0x00);
I2CWriteByte(HX8824_ADDR, 0x96, 0x80);
I2CWriteByte(HX8824_ADDR, 0x97, 0x02);
I2CWriteByte(HX8824_ADDR, 0x98, 0x0D);
I2CWriteByte(HX8824_ADDR, 0x99, 0x02);
I2CWriteByte(HX8824_ADDR, 0x9A, 0x02);
I2CWriteByte(HX8824_ADDR, 0x9B, 0x00);
I2CWriteByte(HX8824_ADDR, 0x9C, 0x23);
I2CWriteByte(HX8824_ADDR, 0x9D, 0x00);
I2CWriteByte(HX8824_ADDR, 0x9E, 0xE0);
I2CWriteByte(HX8824_ADDR, 0x9F, 0x01);
//***************** PLL ********************************************************
I2CWriteByte(HX8824_ADDR, 0xD0, 0x08); // P1
I2CWriteByte(HX8824_ADDR, 0xD1, 0x08); // P2
I2CWriteByte(HX8824_ADDR, 0xD2, 0x0C); // N
I2CWriteByte(HX8824_ADDR, 0xD3, 0xF5); // M: 246 -1
I2CWriteByte(HX8824_ADDR, 0xD4, 0x00); // M
#endif
265 1 //***************************************************************************************
266 1 #if mode6448_3224
// Select source from VGA
bVideo = 0;
S1 = 1;
S2 = 0;
Mode = 3;
I2CWriteByte(HX8824_ADDR, 0x10, 0x1C); // input format select
I2CWriteByte(HX8824_ADDR, 0x11, 0x04);
I2CWriteByte(HX8824_ADDR, 0x20, 0x00);
I2CWriteByte(HX8824_ADDR, 0x21, 0x20);
I2CWriteByte(HX8824_ADDR, 0x22, 0xFF);
I2CWriteByte(HX8824_ADDR, 0x23, 0x0F);
I2CWriteByte(HX8824_ADDR, 0x20, 0x00);
I2CWriteByte(HX8824_ADDR, 0x21, 0x20);
I2CWriteByte(HX8824_ADDR, 0x22, 0xFF);
I2CWriteByte(HX8824_ADDR, 0x23, 0x1F);
I2CWriteByte(HX8824_ADDR, 0x24, 0x00);
I2CWriteByte(HX8824_ADDR, 0x25, 0x00);
I2CWriteByte(HX8824_ADDR, 0x24, 0x00);
I2CWriteByte(HX8824_ADDR, 0x25, 0x04);
I2CWriteByte(HX8824_ADDR, 0xA0, 0xF9);
I2CWriteByte(HX8824_ADDR, 0xA1, 0x00);
I2CWriteByte(HX8824_ADDR, 0xA2, 0x00);
I2CWriteByte(HX8824_ADDR, 0x00, 0x80);
I2CWriteByte(HX8824_ADDR, 0x01, 0x02);
I2CWriteByte(HX8824_ADDR, 0x02, 0xE0);
I2CWriteByte(HX8824_ADDR, 0x03, 0x01);
I2CWriteByte(HX8824_ADDR, 0x90, 0x5A);
I2CWriteByte(HX8824_ADDR, 0x91, 0x03);
I2CWriteByte(HX8824_ADDR, 0x92, 0x3F);
I2CWriteByte(HX8824_ADDR, 0x93, 0x00);
I2CWriteByte(HX8824_ADDR, 0x94, 0x7A);
I2CWriteByte(HX8824_ADDR, 0x95, 0x00);
I2CWriteByte(HX8824_ADDR, 0x96, 0x40);
I2CWriteByte(HX8824_ADDR, 0x97, 0x01);
C51 COMPILER V7.07 HX8824 09/26/2006 08:56:42 PAGE 6
I2CWriteByte(HX8824_ADDR, 0x98, 0x07);
I2CWriteByte(HX8824_ADDR, 0x99, 0x01);
I2CWriteByte(HX8824_ADDR, 0x9A, 0x03);
I2CWriteByte(HX8824_ADDR, 0x9B, 0x00);
I2CWriteByte(HX8824_ADDR, 0x9C, 0x12);
I2CWriteByte(HX8824_ADDR, 0x9D, 0x00);
I2CWriteByte(HX8824_ADDR, 0x9E, 0xF0);
I2CWriteByte(HX8824_ADDR, 0x9F, 0x00);
//***************** PLL ********************************************************
I2CWriteByte(HX8824_ADDR, 0xD0, 0x1C); // P1
I2CWriteByte(HX8824_ADDR, 0xD1, 0x0E); // P2
I2CWriteByte(HX8824_ADDR, 0xD2, 0x07); // N
I2CWriteByte(HX8824_ADDR, 0xD3, 0x04); // M: 261 -1
I2CWriteByte(HX8824_ADDR, 0xD4, 0x01); // M
#endif
316 1 //*************************************************************************************
317 1 #if mode7224_8060
bVideo = 1;
S1 = 0;
S2 = 1;
Mode = 4;
I2CWriteByte(HX8824_ADDR, 0x10, 0x1C); // input format select
//I2CWriteByte(HX8824_ADDR, 0x11, 0x0C); // 656
I2CWriteByte(HX8824_ADDR, 0x11, 0x0F); //601
I2CWriteByte(HX8824_ADDR, 0x20, 0x7A);
I2CWriteByte(HX8824_ADDR, 0x21, 0x06);
I2CWriteByte(HX8824_ADDR, 0x22, 0xFF);
I2CWriteByte(HX8824_ADDR, 0x23, 0x0F);
I2CWriteByte(HX8824_ADDR, 0x20, 0x65);
I2CWriteByte(HX8824_ADDR, 0x21, 0x0E);
I2CWriteByte(HX8824_ADDR, 0x22, 0xFF);
I2CWriteByte(HX8824_ADDR, 0x23, 0x1F);
I2CWriteByte(HX8824_ADDR, 0x24, 0x00);
I2CWriteByte(HX8824_ADDR, 0x25, 0x00);
I2CWriteByte(HX8824_ADDR, 0x24, 0x00);
I2CWriteByte(HX8824_ADDR, 0x25, 0x04);
I2CWriteByte(HX8824_ADDR, 0xA0, 0xeb);
I2CWriteByte(HX8824_ADDR, 0xA1, 0x05);
I2CWriteByte(HX8824_ADDR, 0xA2, 0x00);
I2CWriteByte(HX8824_ADDR, 0x00, 0xd0);
I2CWriteByte(HX8824_ADDR, 0x01, 0x02);
I2CWriteByte(HX8824_ADDR, 0x02, 0xF3);
I2CWriteByte(HX8824_ADDR, 0x03, 0x00);
I2CWriteByte(HX8824_ADDR, 0x90, 0x03);
I2CWriteByte(HX8824_ADDR, 0x91, 0x04);
I2CWriteByte(HX8824_ADDR, 0x92, 0x48);
I2CWriteByte(HX8824_ADDR, 0x93, 0x00);
I2CWriteByte(HX8824_ADDR, 0x94, 0x90);
I2CWriteByte(HX8824_ADDR, 0x95, 0x00);
I2CWriteByte(HX8824_ADDR, 0x96, 0x20);
I2CWriteByte(HX8824_ADDR, 0x97, 0x03);
I2CWriteByte(HX8824_ADDR, 0x98, 0x92);
I2CWriteByte(HX8824_ADDR, 0x99, 0x02);
I2CWriteByte(HX8824_ADDR, 0x9A, 0x13);
I2CWriteByte(HX8824_ADDR, 0x9B, 0x00);
I2CWriteByte(HX8824_ADDR, 0x9C, 0x26);
I2CWriteByte(HX8824_ADDR, 0x9D, 0x00);
I2CWriteByte(HX8824_ADDR, 0x9E, 0x58);
I2CWriteByte(HX8824_ADDR, 0x9F, 0x02);
//***************** PLL ********************************************************
I2CWriteByte(HX8824_ADDR, 0xD0, 0x08); // P1
I2CWriteByte(HX8824_ADDR, 0xD1, 0x09); // P2
C51 COMPILER V7.07 HX8824 09/26/2006 08:56:42 PAGE 7
I2CWriteByte(HX8824_ADDR, 0xD2, 0x09); // N
I2CWriteByte(HX8824_ADDR, 0xD3, 0x2B); // M: 300 -1
I2CWriteByte(HX8824_ADDR, 0xD4, 0x01); // M
//I2CWriteByte(SAA7111_ADDR, 0x08, 0xC8);
#endif
368 1 //*************************************************************************************
369 1 #if mode7224_8048
Mode = 6;
bVideo = 1;
S1 = 0;
S2 = 1;
Mode = 5;
// Select Input Mux, For VIDEO Input
I2CWriteByte(HX8824_ADDR, 0x10, 0x1C); // Use external HS,VS,DE; port A
//I2CWriteByte(HX8824_ADDR, 0x11, 0x0C); // 656
I2CWriteByte(HX8824_ADDR, 0x11, 0x0F); //656
//I2CWriteByte(HX8824_ADDR, 0x11, 0x0B); // CCIR601, VS and HS are postive
// Set scaling ratio
I2CWriteByte(HX8824_ADDR, 0x20, 0x19);
I2CWriteByte(HX8824_ADDR, 0x21, 0x08);
I2CWriteByte(HX8824_ADDR, 0x22, 0xFF);
I2CWriteByte(HX8824_ADDR, 0x23, 0x0F);
I2CWriteByte(HX8824_ADDR, 0x20, 0x65);
I2CWriteByte(HX8824_ADDR, 0x21, 0x0E);
I2CWriteByte(HX8824_ADDR, 0x22, 0xFF);
I2CWriteByte(HX8824_ADDR, 0x23, 0x1F);
// DTV ratio
/* I2CWriteByte(HX8824_ADDR, 0x20, 0x00);
I2CWriteByte(HX8824_ADDR, 0x21, 0x08);
I2CWriteByte(HX8824_ADDR, 0x22, 0xFF);
I2CWriteByte(HX8824_ADDR, 0x23, 0x0F);
I2CWriteByte(HX8824_ADDR, 0x20, 0x00);
I2CWriteByte(HX8824_ADDR, 0x21, 0x0E);
I2CWriteByte(HX8824_ADDR, 0x22, 0xFF);
I2CWriteByte(HX8824_ADDR, 0x23, 0x1F);
*/
// Set Border
I2CWriteByte(HX8824_ADDR, 0x24, 0x00);
I2CWriteByte(HX8824_ADDR, 0x25, 0x00);
I2CWriteByte(HX8824_ADDR, 0x24, 0x00);
I2CWriteByte(HX8824_ADDR, 0x25, 0x04);
// Set VS reset
//I2CWriteByte(HX8824_ADDR, 0xA0, 0x34); //B1
//I2CWriteByte(HX8824_ADDR, 0xA1, 0x1C); //11
//I2CWriteByte(HX8824_ADDR, 0xA2, 0x00);
//I2CWriteByte(HX8824_ADDR, 0xA0, 0x34); //B1 ok for PVI
//I2CWriteByte(HX8824_ADDR, 0xA1, 0x09); //11
//I2CWriteByte(HX8824_ADDR, 0xA2, 0x00);
I2CWriteByte(HX8824_ADDR, 0xA0, 0x36); //B1 ok for hx8819
I2CWriteByte(HX8824_ADDR, 0xA1, 0x06); //11
I2CWriteByte(HX8824_ADDR, 0xA2, 0x00);
// Set input timing
I2CWriteByte(HX8824_ADDR, 0x00, 0xD0);
I2CWriteByte(HX8824_ADDR, 0x01, 0x02);
I2CWriteByte(HX8824_ADDR, 0x02, 0xF3);
I2CWriteByte(HX8824_ADDR, 0x03, 0x00);
//I2CWriteByte(HX8824_ADDR, 0x14, 0x00);
C51 COMPILER V7.07 HX8824 09/26/2006 08:56:42 PAGE 8
//I2CWriteByte(HX8824_ADDR, 0x15, 0x00);
//I2CWriteByte(HX8824_ADDR, 0x16, 0x00);
//I2CWriteByte(HX8824_ADDR, 0x17, 0x00);
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