intprg.src

瑞萨7709系列高档单片机串口通信的工程文件

;------------------------------------------------------------------------
;                                                                       |
;   FILE        :intprg.src                                             |
;   DATE        :Thu, Nov 23, 2006                                      |
;   DESCRIPTION :Interrupt Program                                      |
;   CPU TYPE    :SH7709S                                                |
;                                                                       |
;   This file is generated by Renesas Project Generator (Ver.3.1).      |
;                                                                       |
;------------------------------------------------------------------------
                  


        .include        "vect.inc"
        .section        IntPRG,code

        ;H'040 TLB miss/invalid (load)
_INT_TLBMiss_Load
        ;H'060 TLB miss/invalid (store)
_INT_TLBMiss_Store
        ;H'080 Initial page write
_INT_TLBInitial_Page
        ;H'0A0 TLB protect (load)
_INT_TLBProtect_Load
        ;H'0C0 TLB protect (store)
_INT_TLBProtect_Store
        ;H'0E0 Address error (load)
_INT_Address_load
        ;H'100 Address error (store)
_INT_Address_store
        ;H'120 Reserved
_INT_Reserved1
        ;H'140 Reserved
_INT_Reserved2
        ;H'160 TRAPA
_INT_TRAPA
        ;H'180 Illegal code
_INT_Illegal_code
        ;H'1A0 Illegal slot
_INT_Illegal_slot
        ;H'1C0 Nonmaskable interrupt
_INT_NMI
        ;H'1E0 User breakpoint trap
_INT_User_Break
        ;H'200 External hardware interrupt
_INT_Extern_0000
        ;H'220 External hardware interrupt
_INT_Extern_0001
        ;H'240 External hardware interrupt
_INT_Extern_0010
        ;H'260 External hardware interrupt
_INT_Extern_0011
        ;H'280 External hardware interrupt
_INT_Extern_0100
        ;H'2A0 External hardware interrupt
_INT_Extern_0101
        ;H'2C0 External hardware interrupt
_INT_Extern_0110
        ;H'2E0 External hardware interrupt
_INT_Extern_0111
        ;H'300 External hardware interrupt
_INT_Extern_1000
        ;H'320 External hardware interrupt
_INT_Extern_1001
        ;H'340 External hardware interrupt
_INT_Extern_1010
        ;H'360 External hardware interrupt
_INT_Extern_1011
        ;H'380 External hardware interrupt
_INT_Extern_1100
        ;H'3A0 External hardware interrupt
_INT_Extern_1101
        ;H'3C0 External hardware interrupt
_INT_Extern_1110
        ;H'3E0 Reserved
_INT_Reserved3E0
        ;H'400 TMU TUNI0
_INT_TMU_TUNI0
        ;H'420 TMU TUNI1
_INT_TMU_TUNI1
        ;H'440 TMU TUNI2
_INT_TMU_TUNI2
        ;H'460 TMU TICPI2
_INT_TMU_TICPI2
        ;H'480 RTC ATI
_INT_RTC_ATI
        ;H'4A0 RTC PRI
_INT_RTC_PRI
        ;H'4C0 RTC CUI
_INT_RTC_CUI
        ;H'4E0 SCI ERI
_INT_SCI_ERI
        ;H'500 SCI RXI
_INT_SCI_RXI
        ;H'520 SCI TXI
_INT_SCI_TXI
        ;H'540 SCI TEI
_INT_SCI_TEI
        ;H'560 CPG ITI
_INT_CPG_ITI
        ;H'580 BSC RCMI
_INT_BSC_RCMI
        ;H'5A0 BSC ROVI
_INT_BSC_ROVI
        ;H'5C0 Reserved
_INT_Reserved5C0
        ;H'5E0 Reserved
_INT_Reserved5E0
        ;H'600 IRQ0
_INT_IRQ0
        ;H'620 IRQ1
_INT_IRQ1
        ;H'640 IRQ2
_INT_IRQ2
        ;H'660 IRQ3
_INT_IRQ3
        ;H'680 IRQ4
_INT_IRQ4
        ;H'6A0 IRQ5
_INT_IRQ5
        ;H'6C0 Reserved
_INT_Reserved6C0
        ;H'6E0 Reserved
_INT_Reserved6E0
        ;H'700 PINT0_7
_INT_PINT0_7
        ;H'720 PINT8_15
_INT_PINT8_15
        ;H'740 Reserved
_INT_Reserved740
        ;H'760 Reserved
_INT_Reserved760
        ;H'780 Reserved
_INT_Reserved780
        ;H'7A0 Reserved
_INT_Reserved7A0
        ;H'7C0 Reserved
_INT_Reserved7C0
        ;H'7E0 Reserved
_INT_Reserved7E0
        ;H'800 DMAC DEI0
_INT_DMAC_DEI0
        ;H'820 DMAC DEI1
_INT_DMAC_DEI1
        ;H'840 DMAC DEI2
_INT_DMAC_DEI2
        ;H'860 DMAC DEI3
_INT_DMAC_DEI3
        ;H'880 IrDA ERI1
_INT_IrDA_ERI1
        ;H'8A0 IrDA RXI1
_INT_IrDA_RXI1
        ;H'8C0 IrDA BRI1
_INT_IrDA_BRI1
        ;H'8E0 IrDA TXI1
_INT_IrDA_TXI1
        ;H'900 SCIF ERI2
_INT_SCIF_ERI2
        ;H'920 SCIF RXI2
_INT_SCIF_RXI2
        ;H'940 SCIF BRI2
_INT_SCIF_BRI2
        ;H'960 SCIF TXI2
_INT_SCIF_TXI2
        ;H'980 ADC ADI
_INT_ADC_ADI
    sleep
    nop
    .end