📄 lcm.fit.rpt
字号:
; 20 ; 2 ;
; 21 ; 2 ;
+----------------------------------------------+------------------------------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+--------------------------+
; Option ; Setting ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As output driving ground ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
+----------------------------+
; Advanced Data - General ;
+--------------------+-------+
; Name ; Value ;
+--------------------+-------+
; Status Code ; 0 ;
; Desired User Slack ; 0 ;
; Fit Attempts ; 1 ;
+--------------------+-------+
+--------------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation ;
+--------------------------------------------------------------------------------+-----------------+
; Name ; Value ;
+--------------------------------------------------------------------------------+-----------------+
; Auto Fit Point 1 - Fit Attempt 1 ; ff ;
; Mid Wire Use - Fit Attempt 1 ; 18 ;
; Mid Slack - Fit Attempt 1 ; -10211 ;
; Internal Atom Count - Fit Attempt 1 ; 183 ;
; LE/ALM Count - Fit Attempt 1 ; 183 ;
; LAB Count - Fit Attempt 1 ; 19 ;
; Outputs per Lab - Fit Attempt 1 ; 5.263 ;
; Inputs per LAB - Fit Attempt 1 ; 12.000 ;
; Global Inputs per LAB - Fit Attempt 1 ; 1.000 ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1 ; 0:19 ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1 ; 0:7;1:7;2:5 ;
; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:7;1:6;2:5;3:1 ;
; LAB Constraint 'un-route combination' - Fit Attempt 1 ; 0:7;1:6;2:5;3:1 ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1 ; 0:7;1:4;2:2;3:6 ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1 ; 0:7;1:4;2:2;3:6 ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1 ; 0:17;1:2 ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1 ; 0:19 ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1 ; 0:7;1:9;2:3 ;
; LAB Constraint 'global control signals' - Fit Attempt 1 ; 0:7;1:5;2:7 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:7;1:8;2:4 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1 ; 0:19 ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1 ; 0:7;1:8;2:4 ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1 ; 0:15;1:4 ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1 ; 0:1;1:18 ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:19 ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:19 ;
; LEs in Chains - Fit Attempt 1 ; 0 ;
; LEs in Long Chains - Fit Attempt 1 ; 0 ;
; LABs with Chains - Fit Attempt 1 ; 0 ;
; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;
; Time - Fit Attempt 1 ; 0 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.015 ;
+--------------------------------------------------------------------------------+-----------------+
+----------------------------------------------+
; Advanced Data - Placement ;
+-------------------------------------+--------+
; Name ; Value ;
+-------------------------------------+--------+
; Auto Fit Point 2 - Fit Attempt 1 ; ff ;
; Early Wire Use - Fit Attempt 1 ; 6 ;
; Early Slack - Fit Attempt 1 ; -15624 ;
; Auto Fit Point 3 - Fit Attempt 1 ; ff ;
; Auto Fit Point 4 - Fit Attempt 1 ; ff ;
; Mid Wire Use - Fit Attempt 1 ; 10 ;
; Mid Slack - Fit Attempt 1 ; -11268 ;
; Late Wire Use - Fit Attempt 1 ; 11 ;
; Late Slack - Fit Attempt 1 ; -11268 ;
; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
; Time - Fit Attempt 1 ; 0 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.063 ;
+-------------------------------------+--------+
+----------------------------------------------+
; Advanced Data - Routing ;
+-------------------------------------+--------+
; Name ; Value ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1 ; -9650 ;
; Early Wire Use - Fit Attempt 1 ; 10 ;
; Peak Regional Wire - Fit Attempt 1 ; 9 ;
; Mid Slack - Fit Attempt 1 ; -11449 ;
; Late Slack - Fit Attempt 1 ; -10383 ;
; Late Slack - Fit Attempt 1 ; -10383 ;
; Late Wire Use - Fit Attempt 1 ; 13 ;
; Time - Fit Attempt 1 ; 0 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.061 ;
+-------------------------------------+--------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Tue Apr 14 15:24:31 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off lcm -c lcm
Info: Selected device EPM570T144C5 for design "lcm"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EPM570T144I5 is compatible
Info: Device EPM1270T144C5 is compatible
Info: Device EPM1270T144I5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted some destinations of signal "clk" to use Global clock in PIN 18
Info: Destination "ena" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "rst" to use Global clock
Info: Destination "ctrl[1]~reg0" may be non-global or may not use global clock
Info: Destination "cs[0]~reg0" may be non-global or may not use global clock
Info: Destination "cs[1]~reg0" may be non-global or may not use global clock
Info: Destination "data_out[0]~205" may be non-global or may not use global clock
Info: Destination "data[0]~388" may be non-global or may not use global clock
Info: Pin "rst" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
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