ad.vhd

来自「代码是12864的vhdl驱动程序 并带有字库」· VHDL 代码 · 共 47 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity  ad is
  port(
        clk:in std_logic;
        din:out std_logic;
        sck:out std_logic;
         cs:out std_logic
         );
end entity;

architecture u of ad is
 signal mosi: std_logic;
 signal  count  : STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL clk_10 : STD_LOGIC;
begin
process(clk)
begin
  if clk'event and clk='1' then
    if (count="11000110")  then 
              count<=(others=>'0');
     clk_10<=not clk_10;
            else
              count <= count +1;
            end if ;
            end if;
end process;
 sck <= clk_10;

process (clk_10)
 constant st: std_logic_vector(7 downto 0):="10000000";
  variable n: integer range 7 to 0;
begin
 n:=7;
  cs<='0';
if clk_10'event and clk_10='1' then
  mosi<=st(n); 
  din<=mosi;
   n:=n-1;
   end if; 
  cs<='1';
end process;
end architecture u;